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IBM z10 (microprocessor)
Encyclopedia
The z10 is a microprocessor
chip made by IBM
for their System z10
mainframe computer
s, released February 26, 2008. It was called "z6" during development.
z/Architecture
and has four cores. Each core has a 64 KB
L1 instruction cache
, a 128 KB L1 data cache and a 3 MB
L2 cache
(called the L1.5 cache by IBM). Finally, there is a 24 MB shared L3 cache (referred to as the L2 cache by IBM).
The chip measures 21.7×20.0 mm and consists of 993 million transistor
s fabricated in IBM's 65 nm SOI
fabrication process (CMOS 11S), supporting speeds of 4.4 GHz
and above – more than twice the clock speed as former mainframes – with a 15 FO4
cycle.
Each z10 chip has two 48 GB
/s (48 billion byte
s per second) SMP hub ports, four 13 GB/s memory ports, two 17 GB/s I/O ports, and 8765 contacts.
The z10 processor was co-developed with and shares many design traits with the POWER6
processor, such as fabrication technology, logic design, execution unit
, floating-point units, bus technology (GX bus) and pipeline
design style, i.e., a high frequency, low latency, deep (14 stages in the z10), in-order pipeline.
However, the processors are quite dissimilar in other respects, such as cache hierarchy and coherency
, SMP
topology and protocol, and chip organization. The different ISA
s result in very different cores – there are 894 unique z10 instructions, 75% of which are implemented entirely in hardware. The z/Architecture is a CISC
architecture, backwards compatible to the IBM System/360 architecture from the 1960s.
Additions to the z/Architecture from the previous z9 EC processor include:
Error detection and recovery is emphasized, with error-correcting code (ECC) on L2 and L3 caches and buffers, and extensive parity checking elsewhere; in all over 20,000 error checkers on the chip. Processor state is buffered in a way that allows precise core retry for almost all hardware errors.
(SMP), there is a dedicated companion chip called the SMP Hub Chip or Storage Control (SC) that adds 24 MB off-die L3 cache
and lets it communicate with other z10 processors and Hub Chips at 48 GB/s. The Hub Chip consists of 1.6 billion transistors and measures 20.8×21.4 mm, with 7984 interconnects. The design allows each processor to share cache across two Hub Chips, for a potential total of 48 MB of shared L3 cache.
On the System z10 Enterprise Class (EC) the z10 processors and the Storage Control (SC) chips are mounted on multi-chip module
s (MCMs). Each z10 EC system can have up to four MCMs. One MCM consists of five z10 processors and two SC chips, totaling in seven chips per MCM. Due to redundancy, manufacturing issues, and other operating features, not all cores are available to the customer. The System z10 EC models E12, E26, E40 and E56, the MCMs have 17 available cores (one, two, three and four MCMs respectively), and the model E64 have one MCM with 17 cores, and three with 20 cores.
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
chip made by IBM
IBM
International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
for their System z10
IBM System z10
IBM System z10 is a line of IBM mainframes. The z10 Enterprise Class was announced on February 26, 2008. On October 21, 2008, IBM announced the z10 Business Class , a scaled down version of the z10 EC...
mainframe computer
Mainframe computer
Mainframes are powerful computers used primarily by corporate and governmental organizations for critical applications, bulk data processing such as census, industry and consumer statistics, enterprise resource planning, and financial transaction processing.The term originally referred to the...
s, released February 26, 2008. It was called "z6" during development.
Description
The processor implements the CISCComplex instruction set computer
A complex instruction set computer , is a computer where single instructions can execute several low-level operations and/or are capable of multi-step operations or addressing modes within single instructions...
z/Architecture
Z/Architecture
z/Architecture, initially and briefly called ESA Modal Extensions , refers to IBM's 64-bit computing architecture for IBM mainframe computers. IBM introduced its first z/Architecture-based system, the zSeries Model 900, in late 2000. Later z/Architecture systems include the IBM z800, z990, z890,...
and has four cores. Each core has a 64 KB
Kilobyte
The kilobyte is a multiple of the unit byte for digital information. Although the prefix kilo- means 1000, the term kilobyte and symbol KB have historically been used to refer to either 1024 bytes or 1000 bytes, dependent upon context, in the fields of computer science and information...
L1 instruction cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
, a 128 KB L1 data cache and a 3 MB
Megabyte
The megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: bytes generally for computer memory; and one million bytes generally for computer storage. The IEEE Standards Board has decided that "Mega will mean 1 000...
L2 cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
(called the L1.5 cache by IBM). Finally, there is a 24 MB shared L3 cache (referred to as the L2 cache by IBM).
The chip measures 21.7×20.0 mm and consists of 993 million transistor
Transistor
A transistor is a semiconductor device used to amplify and switch electronic signals and power. It is composed of a semiconductor material with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals changes the current...
s fabricated in IBM's 65 nm SOI
Silicon on insulator
Silicon on insulator technology refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance...
fabrication process (CMOS 11S), supporting speeds of 4.4 GHz
GHZ
GHZ or GHz may refer to:# Gigahertz .# Greenberger-Horne-Zeilinger state — a quantum entanglement of three particles.# Galactic Habitable Zone — the region of a galaxy that is favorable to the formation of life....
and above – more than twice the clock speed as former mainframes – with a 15 FO4
FO4
Fan-out of 4 is a process independent delay metric used in digital CMOS technologies.Fan out = Cload / CinCload = total MOS gate capacitance driven by the logic gate under considerationCin = the MOS gate capacitance of the logic gate under consideration...
cycle.
Each z10 chip has two 48 GB
Gigabyte
The gigabyte is a multiple of the unit byte for digital information storage. The prefix giga means 109 in the International System of Units , therefore 1 gigabyte is...
/s (48 billion byte
Byte
The byte is a unit of digital information in computing and telecommunications that most commonly consists of eight bits. Historically, a byte was the number of bits used to encode a single character of text in a computer and for this reason it is the basic addressable element in many computer...
s per second) SMP hub ports, four 13 GB/s memory ports, two 17 GB/s I/O ports, and 8765 contacts.
The z10 processor was co-developed with and shares many design traits with the POWER6
POWER6
The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.03. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor...
processor, such as fabrication technology, logic design, execution unit
Execution unit
In computer engineering, an execution unit is a part of a CPU that performs the operations and calculations called for by the Branch Unit, which receives data from the CPU...
, floating-point units, bus technology (GX bus) and pipeline
Instruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
design style, i.e., a high frequency, low latency, deep (14 stages in the z10), in-order pipeline.
However, the processors are quite dissimilar in other respects, such as cache hierarchy and coherency
Cache coherency
In computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...
, SMP
Symmetric multiprocessing
In computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...
topology and protocol, and chip organization. The different ISA
Instruction set
An instruction set, or instruction set architecture , is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O...
s result in very different cores – there are 894 unique z10 instructions, 75% of which are implemented entirely in hardware. The z/Architecture is a CISC
Complex instruction set computer
A complex instruction set computer , is a computer where single instructions can execute several low-level operations and/or are capable of multi-step operations or addressing modes within single instructions...
architecture, backwards compatible to the IBM System/360 architecture from the 1960s.
Additions to the z/Architecture from the previous z9 EC processor include:
- 50+ new instructions for improved code efficiency
- software/hardware cache optimizations
- support for 1 MB page frames
- decimal floating point fully implemented in hardware.
Error detection and recovery is emphasized, with error-correcting code (ECC) on L2 and L3 caches and buffers, and extensive parity checking elsewhere; in all over 20,000 error checkers on the chip. Processor state is buffered in a way that allows precise core retry for almost all hardware errors.
Storage Control
Even though the z10 processor has on-die facilities for symmetric multiprocessingSymmetric multiprocessing
In computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...
(SMP), there is a dedicated companion chip called the SMP Hub Chip or Storage Control (SC) that adds 24 MB off-die L3 cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
and lets it communicate with other z10 processors and Hub Chips at 48 GB/s. The Hub Chip consists of 1.6 billion transistors and measures 20.8×21.4 mm, with 7984 interconnects. The design allows each processor to share cache across two Hub Chips, for a potential total of 48 MB of shared L3 cache.
Multi-chip module
Multi-Chip Module
A multi-chip module is a specialized electronic package where multiple integrated circuits , semiconductor dies or other discrete components are packaged onto a unifying substrate, facilitating their use as a single component...
s (MCMs). Each z10 EC system can have up to four MCMs. One MCM consists of five z10 processors and two SC chips, totaling in seven chips per MCM. Due to redundancy, manufacturing issues, and other operating features, not all cores are available to the customer. The System z10 EC models E12, E26, E40 and E56, the MCMs have 17 available cores (one, two, three and four MCMs respectively), and the model E64 have one MCM with 17 cores, and three with 20 cores.
See also
- z/ArchitectureZ/Architecturez/Architecture, initially and briefly called ESA Modal Extensions , refers to IBM's 64-bit computing architecture for IBM mainframe computers. IBM introduced its first z/Architecture-based system, the zSeries Model 900, in late 2000. Later z/Architecture systems include the IBM z800, z990, z890,...
- IBM System z
- IBM System z10IBM System z10IBM System z10 is a line of IBM mainframes. The z10 Enterprise Class was announced on February 26, 2008. On October 21, 2008, IBM announced the z10 Business Class , a scaled down version of the z10 EC...
- z/OSZ/OSz/OS is a 64-bit operating system for mainframe computers, produced by IBM. It derives from and is the successor to OS/390, which in turn followed a string of MVS versions.Starting with earliest:*OS/VS2 Release 2 through Release 3.8...
- POWER6POWER6The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.03. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor...
- Mainframe computerMainframe computerMainframes are powerful computers used primarily by corporate and governmental organizations for critical applications, bulk data processing such as census, industry and consumer statistics, enterprise resource planning, and financial transaction processing.The term originally referred to the...