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Wishbone (computer bus)
Encyclopedia
The Wishbone Bus is an open source hardware
computer bus
intended to let the parts of an integrated circuit
communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores
project.
A large number of open-source designs for CPU
s, and auxiliary computer peripherals have now been released with Wishbone interfaces. Many can be found at OpenCores
, a foundation that attempts to make open-source hardware designs available.
Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels.
This ambiguity is intentional. Wishbone is made to let designers combine several designs written in Verilog
, VHDL or some other logic-description language for electronic design automation
. Wishbone provides a standard way for designers to combine these hardware logic designs (called "cores").
Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated combinatorially
for maximum performance. Wishbone permits addition of a "tag bus" to describe the data. But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags.
Wishbone is open source
, which makes it easy for engineers and hobbyists to share public domain designs for hardware logic on the Internet. To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples of preexisting art, to prove its concepts are in the public domain.
A device does not conform to the Wishbone specification unless it includes a data sheet that describes what it does, bus width, utilization, etc. Promoting reuse of a design requires the data sheet. Making a design reusable in turn makes it easier to share with others.
es. In the more exotic topologies, Wishbone requires a bus controller or arbiter, but devices still maintain the same interface.
Open source hardware
Open source hardware consists of physical artifacts of technology designed and offered in the same manner as free and open source software . Open source hardware is part of the open source culture movement and applies a like concept to a variety of components. The term usually means that...
computer bus
Computer bus
In computer architecture, a bus is a subsystem that transfers data between components inside a computer, or between computers.Early computer buses were literally parallel electrical wires with multiple connections, but the term is now used for any physical arrangement that provides the same...
intended to let the parts of an integrated circuit
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores
OpenCores
OpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...
project.
A large number of open-source designs for CPU
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
s, and auxiliary computer peripherals have now been released with Wishbone interfaces. Many can be found at OpenCores
OpenCores
OpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...
, a foundation that attempts to make open-source hardware designs available.
Wishbone is intended as a "logic bus". It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels.
This ambiguity is intentional. Wishbone is made to let designers combine several designs written in Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
, VHDL or some other logic-description language for electronic design automation
Electronic design automation
Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
. Wishbone provides a standard way for designers to combine these hardware logic designs (called "cores").
Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated combinatorially
Combinational logic
In digital circuit theory, combinational logic is a type of digital logic which is implemented by boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the...
for maximum performance. Wishbone permits addition of a "tag bus" to describe the data. But reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags.
Wishbone is open source
Open source
The term open source describes practices in production and development that promote access to the end product's source materials. Some consider open source a philosophy, others consider it a pragmatic methodology...
, which makes it easy for engineers and hobbyists to share public domain designs for hardware logic on the Internet. To prevent preemption of its technologies by aggressive patenting, the Wishbone specification includes examples of preexisting art, to prove its concepts are in the public domain.
A device does not conform to the Wishbone specification unless it includes a data sheet that describes what it does, bus width, utilization, etc. Promoting reuse of a design requires the data sheet. Making a design reusable in turn makes it easier to share with others.
Wishbone Topologies
Wishbone adapts well to common topologies such as point-to-point, many-to-many (i.e. the classic bus system), hierarchical, or even switched fabrics such as crossbar switchCrossbar switch
In electronics, a crossbar switch is a switch connecting multiple inputs to multiple outputs in a matrix manner....
es. In the more exotic topologies, Wishbone requires a bus controller or arbiter, but devices still maintain the same interface.
Comparisons
Wishbone Control Signals Compared to Other SOC Bus Standards| Wishbone | Avalon Bus | Description |
|---|---|---|
| cyc | |
indicates that a valid bus cycle is in progress |
| stb | = chipselect | indicates a valid data transfer cycle |
| we | = !write_n and read_n | indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles. |
| ack | = !waitrequest | indicates the termination of a normal bus cycle by slave device. |
| Avalon Bus | Wishbone | Description |
|---|---|---|
| chipselect | = stb | indicates that slave device is selected. |
| write_n | = !(cyc and we) | indicated that master requests to write to slave device. |
| read_n | = !(cyc and !we) | indicated that master requests to read from slave device. |
| waitrequest | = !ack | indicates that slave requests that master wait. |
Competitors
- Avalon Bus
- AMBAAdvanced Microcontroller Bus ArchitectureThe Advanced Microcontroller Bus Architecture is used as the on-chip bus in system-on-a-chip designs. Since its inception, the scope of AMBA has gone far beyond microcontroller devices, and is now widely used on a range of ASIC and SoC parts including applications processors used in modern...
/ AHB (AMBA High-Speed Bus) - IBMIBMInternational Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
CoreConnectCoreConnectCoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip designs. Designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices...
bus technology - PLBCoreConnectCoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip designs. Designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices...
Processor local Bus (part of CoreConnect) - OPBCoreConnectCoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip designs. Designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices...
On-chip Peripheral Bus (part of CoreConnect) - OCPOpen Core Protocol (OCP)The Open Core Protocol is an openly licensed, core-centric protocol intended to meet contemporary system level integration challenges. OCP defines a bus-independent, configurable and scalable interface for on-chip subsystem communications...
Open Core Protocol
External links
- Wishbone Version B3- the PDF specification
- Wishbone Version B4- recently updated PDF specification
- appnote_01- Combining WISHBONE interface signals application note