CoreConnect
Encyclopedia
CoreConnect is a microprocessor
bus-architecture from IBM
for system-on-a-chip
(SoC) designs. Designed to ease the integration and reuse of processor, system, and peripheral cores
within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register
(DCR) bus. High-performance peripherals connect to the high-bandwidth
, low-latency
PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing AMBA
bus architecture, allowing reuse of existing SoC-components.
IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As such it is licensed by over 1500 electronics companies such as Cadence
, Ericsson
, Lucent, Nokia
, Siemens
and Synopsys
.
The CoreConnect is an integral part of IBM's Power Architecture
offering and is used extensively in their PowerPC 4x0 based designs. Xilinx
uses CoreConnect as the infrastructure for all of their embedded processor designs even though only a few are Power Architecture based.
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
bus-architecture from IBM
IBM
International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
for system-on-a-chip
System-on-a-chip
A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
(SoC) designs. Designed to ease the integration and reuse of processor, system, and peripheral cores
Multi-core (computing)
A multi-core processor is a single computing component with two or more independent actual processors , which are the units that read and execute program instructions...
within standard and custom SoC designs. As a standard SoC design point, it serves as the foundation of IBM or non-IBM devices. Elements of this architecture include the processor local bus (PLB), the on-chip peripheral bus (OPB), a bus bridge, and a device control register
Device control register
A device control register is a register that resides in an element of a System-on-a-chip and allows to configure, control and probe this element....
(DCR) bus. High-performance peripherals connect to the high-bandwidth
Bit rate
In telecommunications and computing, bit rate is the number of bits that are conveyed or processed per unit of time....
, low-latency
Latency (engineering)
Latency is a measure of time delay experienced in a system, the precise definition of which depends on the system and the time being measured. Latencies may have different meaning in different contexts.-Packet-switched networks:...
PLB. Slower peripheral cores connect to the OPB, which reduces traffic on the PLB. CoreConnect has bridging capabilities to the competing AMBA
Advanced Microcontroller Bus Architecture
The Advanced Microcontroller Bus Architecture is used as the on-chip bus in system-on-a-chip designs. Since its inception, the scope of AMBA has gone far beyond microcontroller devices, and is now widely used on a range of ASIC and SoC parts including applications processors used in modern...
bus architecture, allowing reuse of existing SoC-components.
IBM makes the CoreConnect bus available as a no-fee, no-royalty architecture to tool-vendors, core IP-companies, and chip-development companies. As such it is licensed by over 1500 electronics companies such as Cadence
Cadence Design Systems
Cadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...
, Ericsson
Ericsson
Ericsson , one of Sweden's largest companies, is a provider of telecommunication and data communication systems, and related services, covering a range of technologies, including especially mobile networks...
, Lucent, Nokia
Nokia
Nokia Corporation is a Finnish multinational communications corporation that is headquartered in Keilaniemi, Espoo, a city neighbouring Finland's capital Helsinki...
, Siemens
Siemens
Siemens may refer toSiemens, a German family name carried by generations of telecommunications industrialists, including:* Werner von Siemens , inventor, founder of Siemens AG...
and Synopsys
Synopsys
Synopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
.
The CoreConnect is an integral part of IBM's Power Architecture
Power Architecture
Power Architecture is a broad term to describe similar RISC instruction sets for microprocessors developed and manufactured by such companies as IBM, Freescale, AMCC, Tundra and P.A. Semi...
offering and is used extensively in their PowerPC 4x0 based designs. Xilinx
Xilinx
Xilinx, Inc. is a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model....
uses CoreConnect as the infrastructure for all of their embedded processor designs even though only a few are Power Architecture based.
Processor Local Bus (PLB)
- General processor local bus
- Synchronous, nonmultiplexed bus
- Separate Read, Write data buses
- Supports concurrent Read, Writes
- Multimaster, programmable-priority, arbitrated bus
- 32-bit up to 64-bit address
- 32-/64-/128-bit implementations (to 256-bit)
- 66/133/183 MHz (32-/64-/128-bit)
- Pipelined, supports early split transactions
- Overlapped arbitration (last cycle)
- Supports fixed, variable-length bursts
- Bus locking
- High bandwidth capabilities, up to 2.9 GBGigabyteThe gigabyte is a multiple of the unit byte for digital information storage. The prefix giga means 109 in the International System of Units , therefore 1 gigabyte is...
/s.
On-chip Peripheral Bus (OPB)
- Peripheral bus for slower devices
- Synchronous, nonmultiplexed bus
- Multimaster, arbitrated bus
- Up to a 64-bit address bus
- Separate 32-bit Read, Write buses
- Pipelined transactions
- Overlapped arbitration (last cycle)
- Supports bursts
- Dynamic bus sizing, 8-, 16-, 32-bit devices
- Single-cycle data transfers
- Bus locking (parking)
Device Control Register (DCR) bus
This bus:- provides fully synchronousSynchronization (computer science)In computer science, synchronization refers to one of two distinct but related concepts: synchronization of processes, and synchronization of data. Process synchronization refers to the idea that multiple processes are to join up or handshake at a certain point, so as to reach an agreement or...
movement of GPRProcessor registerIn computer architecture, a processor register is a small amount of storage available as part of a CPU or other digital processor. Such registers are addressed by mechanisms other than main memory and can be accessed more quickly...
data between CPUCentral processing unitThe central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
and slave logic - functions as a synchronous, nonmultiplexed bus
- has separate buses to read and to write data
- consists of a single-master, multiple-slave bus
- includes a 10-bit address bus
- features 32-bit data buses
- uses two-cycle minimum Read/Write cycles
- utilizes distributed multiplexer architecture
- supports 8-, 16-, and 32-bit devices
- performs single-cycle data transfers