RISC Single Chip
Encyclopedia
The RISC Single Chip, or RSC, is a single-chip microprocessor
developed and fabricated by International Business Machines
(IBM). The RSC was a feature-reduced single-chip implementation of the POWER1
, a multi-chip central processing unit
(CPU) which implemented the POWER
instruction set architecture (ISA). It was used in entry-level workstation
models of the IBM RS/6000 family, such as the Model 220 and 230.
The RSC operated at frequencies of 33 and 45 MHz. It has three execution unit
s: a fixed point unit
, floating point unit
and branch processor; and an 8 KB unified instruction and data cache. Like the POWER1, the memory controller and I/O was tightly integrated, with the functional units responsible for the functions: a memory interface unit and sequencer unit; residing on the same die as the processor. The RSC contains nine functional units, and these other functional units included the memory management unit
, COP unit, instruction fetch unit and instruction queue and dispatch unit.
The fixed point unit executes integer
instructions, generates addresses in load store operations and some portions of branch instructions. It has a three-stage pipeline
consisting of decode, execute and writeback stages. Some instructions require several cycles in the execute stage before they are completed.
The floating point unit executes floating point
instructions. Unlike the POWER1, the RSC does not have register renaming
capability due to a limited die area in which the unit must fit in. To further save die area, the floating point multiply-add array is 32 bits wide. To perform 64-bit (double-precision) operations, the floating point multiply-add array is double-pumped. The floating point pipeline consists of four stages, decode, multiply, add and writeback.
The RSC has an 8 KB unified cache
instead of the separate instruction and large data caches like the POWER1. The unified cache is two-way set associative and uses a store-through policy with no reload on a store miss and a least recently used (LRU) replacement policy. It has a cache line size of 64 bytes, and each cache line is sectored into four quadwords (16 bytes), with each quadword given its own valid bit in the cache directory. During each cycle, four words can be read from it and two doublewords can be written to it.
The memory data bus is 72 bits wide, with a 64 bits used for the data path and 8 bits used for error correcting code (ECC). The memory interface unit manages the bus and performs ECC checks on data coming into the processor. The ECC logic is capable of correcting single-bit errors. Compared to the POWER1, the RSC memory data bus is narrower and uses industry standard SIMM
s instead of custom memory cards.
The RSC contained approximately one million transistors on a 14.9 mm by 15.2 mm (226.48 mm2) die fabricated by IBM in a complementary metal-oxide semiconductor
(CMOS) process with a minimal feature size of 0.8 μm and three levels of wiring. It is packaged in a 36 mm by 36 mm ceramic pin grid array
module which had 201 signal pins. It required a 3.6 volt power supply and consumed 4 watts during operation at 33 MHz.
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
developed and fabricated by International Business Machines
IBM
International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
(IBM). The RSC was a feature-reduced single-chip implementation of the POWER1
POWER1
The POWER1 is a multi-chip CPU developed and fabricated by IBM that implemented the POWER instruction set architecture . It was originally known as the “RISC System/6000 CPU” or when an abbreviated form, the “RS/6000 CPU” before introduction of successors required the original name to be replaced...
, a multi-chip central processing unit
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
(CPU) which implemented the POWER
IBM POWER
POWER is a reduced instruction set computer instruction set architecture developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC....
instruction set architecture (ISA). It was used in entry-level workstation
Workstation
A workstation is a high-end microcomputer designed for technical or scientific applications. Intended primarily to be used by one person at a time, they are commonly connected to a local area network and run multi-user operating systems...
models of the IBM RS/6000 family, such as the Model 220 and 230.
The RSC operated at frequencies of 33 and 45 MHz. It has three execution unit
Execution unit
In computer engineering, an execution unit is a part of a CPU that performs the operations and calculations called for by the Branch Unit, which receives data from the CPU...
s: a fixed point unit
Arithmetic logic unit
In computing, an arithmetic logic unit is a digital circuit that performs arithmetic and logical operations.The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers...
, floating point unit
Floating point unit
A floating-point unit is a part of a computer system specially designed to carry out operations on floating point numbers. Typical operations are addition, subtraction, multiplication, division, and square root...
and branch processor; and an 8 KB unified instruction and data cache. Like the POWER1, the memory controller and I/O was tightly integrated, with the functional units responsible for the functions: a memory interface unit and sequencer unit; residing on the same die as the processor. The RSC contains nine functional units, and these other functional units included the memory management unit
Memory management unit
A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...
, COP unit, instruction fetch unit and instruction queue and dispatch unit.
The fixed point unit executes integer
Integer
The integers are formed by the natural numbers together with the negatives of the non-zero natural numbers .They are known as Positive and Negative Integers respectively...
instructions, generates addresses in load store operations and some portions of branch instructions. It has a three-stage pipeline
Instruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
consisting of decode, execute and writeback stages. Some instructions require several cycles in the execute stage before they are completed.
The floating point unit executes floating point
Floating point
In computing, floating point describes a method of representing real numbers in a way that can support a wide range of values. Numbers are, in general, represented approximately to a fixed number of significant digits and scaled using an exponent. The base for the scaling is normally 2, 10 or 16...
instructions. Unlike the POWER1, the RSC does not have register renaming
Register renaming
In computer architecture, register renaming refers to a technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers by those operations.-Problem definition:...
capability due to a limited die area in which the unit must fit in. To further save die area, the floating point multiply-add array is 32 bits wide. To perform 64-bit (double-precision) operations, the floating point multiply-add array is double-pumped. The floating point pipeline consists of four stages, decode, multiply, add and writeback.
The RSC has an 8 KB unified cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
instead of the separate instruction and large data caches like the POWER1. The unified cache is two-way set associative and uses a store-through policy with no reload on a store miss and a least recently used (LRU) replacement policy. It has a cache line size of 64 bytes, and each cache line is sectored into four quadwords (16 bytes), with each quadword given its own valid bit in the cache directory. During each cycle, four words can be read from it and two doublewords can be written to it.
The memory data bus is 72 bits wide, with a 64 bits used for the data path and 8 bits used for error correcting code (ECC). The memory interface unit manages the bus and performs ECC checks on data coming into the processor. The ECC logic is capable of correcting single-bit errors. Compared to the POWER1, the RSC memory data bus is narrower and uses industry standard SIMM
SIMM
A SIMM, or single in-line memory module, is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s. It differs from a dual in-line memory module , the most predominant form of memory module today, in that the contacts on a SIMM are redundant...
s instead of custom memory cards.
The RSC contained approximately one million transistors on a 14.9 mm by 15.2 mm (226.48 mm2) die fabricated by IBM in a complementary metal-oxide semiconductor
CMOS
Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...
(CMOS) process with a minimal feature size of 0.8 μm and three levels of wiring. It is packaged in a 36 mm by 36 mm ceramic pin grid array
Pin grid array
A pin grid array, often abbreviated PGA, is a type of integrated circuit packaging. In a PGA, the package is square or roughly square, and the pins are arranged in a regular array on the underside of the package...
module which had 201 signal pins. It required a 3.6 volt power supply and consumed 4 watts during operation at 33 MHz.
See also
- PowerPC 601 which essentially was a cheaper and less powerful version of RSC with some PowerPCPowerPCPowerPC is a RISC architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM...
instructions added. - RAD6000RAD6000The RAD6000 radiation-hardened single board computer, based on the IBM RISC Single Chip CPU, was manufactured by IBM Federal Systems. IBM Federal Systems was sold to Loral, and by way of acquisition, ended up with Lockheed Martin and is currently a part of BAE Systems...
which is a radiation hardened version of RSC.