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Pentium II
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The Pentium II brand refers to Intel's sixth-generation microarchitecture ("Intel P6") and x86-compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors, the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro CPUs, which contained 5.5 million transistors.
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Encyclopedia
The Pentium II brand refers to Intel's sixth-generation microarchitecture ("Intel P6") and x86-compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors, the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro CPUs, which contained 5.5 million transistors. In early 1999, the Pentium II was superseded by the Pentium III.
In 1998, Intel stratified the Pentium II family by releasing the Pentium II-based Celeron line of processors for low-end workstations and the Pentium II Xeon line for servers and high-end workstations. The Celeron was characterized by a reduced or omitted (in some cases present but disabled) on-die full-speed L2 cache and a 66 MT/s FSB. The Xeon was characterized by a range of full-speed L2 cache (from 512 KiB to 2048 KiB), a 100 MT/s FSB, a different physical interface (Slot 2), and support for symmetric multiprocessing.
Overview
The Pentium II microprocessor was largely based upon the microarchitecture of its predecessor, the Pentium Pro, but with some significant improvements.
Unlike previous Pentium and Pentium Pro processors, the Pentium II CPU was packaged in a slot-based module rather than a CPU socket. The processor and associated components were carried on a daughterboard similar to a typical expansion board within a plastic cartridge. A fixed or removable heatsink was carried on one side, sometimes using its own fan.
This larger package was a compromise allowing Intel to separate the secondary cache from the processor while still keeping it on a closely coupled backside bus. The L2 cache ran at half the processor's clock frequency, unlike the Pentium Pro, whose off die L2 cache ran at the same frequency as the processor. However, the smallest cache size was increased to 512 KiB from the 256 KiB on the Pentium Pro. Off-package cache solved the Pentium Pro's low yields, allowing Intel to introduce the Pentium II at a mainstream price level. This arrangement also allowed Intel to easily vary the amount of L2 cache, thus making it possible to target different market segments with cheaper or more expensive processors and accompanying performance levels.
Intel notably improved 16-bit code execution performance on the Pentium II, an area in which the Pentium Pro was at a notable handicap. Most consumer software of the day was still using at least some 16-bit code, because of a variety of factors. The Pentium II went to 32 KiB of L1 cache, double that of the Pentium Pro, as well. The Pentium II was also the first P6-based CPU to implement the Intel MMX integer SIMD instruction set which had already been introduced on the Pentium MMX.
The Pentium II was basically a more consumer-oriented version of the Pentium Pro. It was cheaper to manufacture because of the separate, slower L2 cache memory. The improved 16-bit performance and MMX support made it a better choice for consumer-level operating systems, such as Windows 9x, and multimedia applications. Combined with the larger L1 cache and improved 16-bit performance, the slower and cheaper L2 cache's performance impact was reduced. General processor performance was increased while costs were cut.
Variants
Klamath
The original Klamath Pentium II microprocessor (Intel product code 80522) ran at 233 and 266 MHz and were produced in a 0.35 µm process. A 300 MHz version was released later in 1997. These CPUs had a 66 MHz front side bus and were initially used on motherboards equipped with the aging Intel 440FX Natoma chipset designed for the Pentium Pro.
In Intel's "Family/Model/Stepping" scheme, Klamath CPUs are family 6, model 3.
Deschutes
The Deschutes core Pentium II (80523), which debuted at 333 MHz in January 1998, was produced with a 0.25 µm process. The 333 MHz variant was the final Pentium CPU that used the older 66 MHz front side bus; all subsequent Deschutes-core models used a 100 MHz FSB. Later in 1998, Pentium IIs running at 266, 300, 350, 400, and 450 MHz were also released. . The Deschutes core supported FXSAVE and FXRSTOR instructions, as opposed to Klamath.
Pentium II-based systems using the Intel 440LX Balboa chipset were the first to utilize the new generation RAM-standard, SDRAM (which replaced EDO RAM), and the AGP graphics bus. Concurrent with the release of Deschutes cores supporting a 100 MHz front side bus was Intel's release of the 440BX Seattle chipset and its related cousins, the 440MX, 440NX, and 440ZX chipsets. Introduction of the 100 MHz front side bus speed resulted in solid performance improvements for the Pentium II lineup.
The Pentium II Xeon was a high-end version, based on the 0.25 µm Deschutes core, intended for use on workstations and servers. Principally, it used a different type of slot (Slot 2), case, board design, and more expensive full-speed custom L2 cache, which was off-die. Versions were produced with 512 KiB, 1 MiB or 2 MiB L2 caches by varying the number of 512 KiB chips incorporated on the board.
In Intel's "Family/Model/Stepping" scheme, Deschutes CPUs are family 6, model 5 and have the part number 80523.
Pentium II OverDrive
In 1998, the 0.25 µm Deschutes core was utilized in the creation of the Pentium II Overdrive processor, which was aimed at allowing corporate Pentium Pro users to upgrade their aging servers. Combining the Deschutes core in a flip-chip package with a 512 KiB full-speed L2 cache chip from the Pentium II Xeon into a Socket 8-compatible module resulted in a 300 or 333 MHz processor that could run on a 60 or 66 MHz front side bus. This combination brought together some of the more attractive aspects of the Pentium II and the Pentium II Xeon: MMX support/improved 16-bit performance and full-speed L2 cache, respectively. The later "Dixon" mobile Pentium II would emulate this combination with 256 KiB of full-speed cache.
In Intel's "Family/Model/Stepping" scheme, the Pentium II OverDrive CPU identifies itself as family 6, model 3, though this is misleading, as it not based on the family 6/model 3 Klamath core. As noted in the Pentium II Processor update documentation from Intel, "Please note that although this processor has a CPUID of 163xh, it uses a Pentium II processor CPUID 065xh processor core."
Tonga
The 0.25 µm Tonga core was the first mobile Pentium II and had all of the features of the desktop models.
In Intel's "Family/Model/Stepping" scheme, Tonga CPUs are family 6, model 5.
Dixon
Later, in 1999, the 0.25 µm Dixon core with 256 KiB of on-die full speed cache was produced for the mobile market. Reviews showed that the Dixon core was the fastest type of Pentium II produced.
In Intel's "Family/Model/Stepping" scheme, Dixon CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the Mendocino Celeron processors.
Core specifications
Desktop
Klamath (80522)
- L1 cache: 16 + 16 KiB (Data + Instructions)
- L2 cache: 512 KiB, as external chips on the CPU module clocked at half the CPU frequency.
- Packaging: Slot 1 module
- MMX
- Front side bus: 66 MHz, GTL+
- VCore: 2.8 V
- Process: 0.35 µm CMOS
- First release: May 7 1997
- Clockrate: 233, 266, 300 MHz
Deschutes (80523)
- L1 cache: 16 + 16 KiB (Data + Instructions)
- L2 cache: 512 KiB, as external chips on the CPU module clocked at half the CPU frequency.
- Packaging: Slot 1 module
- MMX
- Front side bus: 66, 100 MHz, GTL+
- VCore: 2.0 V
- Process: 0.25 µm CMOS
- First release: January 26 1998
- Clockrate: 266 - 450 MHz
- 66 MHz FSB : 266, 300, 333 MHz
- 100 MHz FSB: 350, 400, 450 MHz
Mobile
Tonga (80523)
Mobile Pentium II
- L1 cache: 16 + 16 KiB (Data + Instructions)
- L2 cache: 512 KiB, as external chips on the CPU module clocked at half the CPU frequency.
- Package: MMC-1, MMC-2, Mini-Cartridge
- MMX
- Front side bus: 66 MHz, GTL+
- VCore: 1.6 V
- Process: 0.25 µm CMOS
- First release: June 7 1997
- Clockrate: 233, 266, 300 MHz
Dixon (80524)
Mobile Pentium II PE ("Performance Enhanced")
- L1 cache: 16 + 16 KiB (Data + Instructions)
- L2 cache: 256 KiB, on-die, full speed.
- Package: BGA1, MMC-1, MMC-2, µPGA1
- MMX
- Front side bus: 66, 100 MHz, GTL+
- VCore: 1.5, 1.55, 1.6 V, 2.0 V
- Process: 0.25 µm CMOS
- First release: January 25 1999
- Clockrate: 266 - 400 MHz
See also
External links
Intel datasheets
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