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AVR32
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The AVR32 is a 32-bit RISC microprocessor architecture designed by Atmel. The microprocessor architecture was designed by a handful of people educated at the Norwegian University of Science and Technology, including lead designer Øyvind Strøm, PhD and CPU architect Erik Renno, M.Sc in Atmel's Norwegian design center.
Most instructions are executed single-cycle. The MAC-unit is capable of performing a 32-bit * 16-bit + 48-bit arithmetic operation in two cycles (result latency), with an issue rate (bandwidth) of one cycle.
Any resemblance to the 8-bit AVR is only with respect to the design center (both architectures originated out of Atmel Norway, Trondheim) and some of the debug-tools.
AVR32A microarchitecture is targeted at cost-sensitive applications, and so does not provide dedicated hardware registers for shadowing of register file registers, status and return address in interrupt contexts.
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Encyclopedia
The AVR32 is a 32-bit RISC microprocessor architecture designed by Atmel. The microprocessor architecture was designed by a handful of people educated at the Norwegian University of Science and Technology, including lead designer Øyvind Strøm, PhD and CPU architect Erik Renno, M.Sc in Atmel's Norwegian design center.
Most instructions are executed single-cycle. The MAC-unit is capable of performing a 32-bit * 16-bit + 48-bit arithmetic operation in two cycles (result latency), with an issue rate (bandwidth) of one cycle.
Any resemblance to the 8-bit AVR is only with respect to the design center (both architectures originated out of Atmel Norway, Trondheim) and some of the debug-tools.
Architecture
The AVR32 Architecture consists of several micro-architectures, most notably the AVR32A and AVR32B architectures, which describes fixed additions to the Instruction Set Architecture, configurations of the register file and the use of instruction and data-caches.
The AVR32A microarchitecture is targeted at cost-sensitive applications, and so does not provide dedicated hardware registers for shadowing of register file registers, status and return address in interrupt contexts. This saves chip area at the expense of slower interrupt handling. The AVR32B, on the other hand, is targeted at applications where interrupt latency is important, so it implements dedicated registers to hold these values for interrupts, exceptions and supervisor calls.
The AVR32 architecture supports a Java Virtual Machine hardware implementation.
The AVR32 Instruction Set Architecture consists of 16-bit (compact) and 32-bit (extended) instructions, with several specialized instructions not found in architectures like MIPS32 or ARMv5 or ARMv6 ISA. Several U.S. patents are filed for the AVR32 ISA and design platform.
Just like the AVR 8-bit microcontroller architecture, the AVR32 was designed for extremely efficient code density and performance per clock cycle. Atmel used the independent benchmark consortium EEMBC to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit (THUMB) code and ARMv5 32-bit (ARM) code by as much as 50% on code-size and 3X on performance.
Implementations
The AVR32 architecture is solely used in Atmel's own products. Atmel launched in 2006 the first implementation of the AVR32 architecture: the AVR32 AP core, a 7-stage pipelined, cache-based design platform. This implementation of the AVR32 architecture adds SIMD (single instruction multiple data) DSP (digital signal processing) instructions to the RISC instruction-set, in addition to Java hardware acceleration.
In 2007, Atmel launched the second implementation of the AVR32 architecture: the AVR32 UC core.
The AVR32 UC core uses a three-stage pipelined Harvard architecture specially designed to optimize instruction fetches from on-chip flash memory. The AVR32 UC core shares the same instruction set architecture (ISA) as its AVR32 AP parent, with over 220 modeless instructions available as 16-bit compact and 32-bit extended instructions. The ISA features atomic bit manipulation to control on-chip peripherals and general purpose IOs and fixed point DSP arithmetic.
Devices
AP Core
UC Core
- UC3A Series - devices deliver 91 Dhrystone MIPS (DMIPS) at 66 MHz (1 flash wait-state) and consume 40 mA at 3.3V.
- UC3B Series - deliver 72 Dhrystone MIPS (DMIPS) at 60 MHz and consume 23 mA at 3.3V.
Boards
External links
- contains recent Linux kernel patches and GCC / binutils
- The AVR Freaks AVR32 Forums
- Free real time kernel for AVR32 flash micros
- supports cross-compilation for thousands of packages for the AVR32
- A build-system supporting the cross compilation to AVR32
- Operating System port for AVR32
- Operating System port for AVR32
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