MIPS is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by
MIPS TechnologiesMIPS Technologies, Inc. , formerly MIPS Computer Systems, Inc., is most widely known for developing the MIPS architecture and a series of pioneering RISC chips. MIPS provides processor architectures and cores for digital home, networking and mobile applications.MIPS Computer Systems Inc. was...
(formerly MIPS Computer Systems, Inc.). The early MIPS architectures were 32-bit, and later versions were 64-bit. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations). MIPS32 and MIPS64 define a control register set as well as the instruction set.
Several optional extensions are also available, including
MIPS-3DMIPS-3D is an extension to the MIPS V instruction set architecture that added 13 new instructions for improving the performance of 3D graphics applications...
which is a simple set of floating-point
SIMDSingle instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...
instructions dedicated to common 3D tasks,
MDMXThe MDMX , also known as MaDMaX, is an extension to the MIPS instruction set architecture released in October 1996 at the Microprocessor Forum.- History :...
(MaDMaX) which is a more extensive integer
SIMDSingle instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...
instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room, and MIPS MT, which adds multithreading capability.
Computer architectureIn computer science and engineering, computer architecture is the practical art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals and the formal modelling of those systems....
courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures such as
AlphaAlpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer instruction set architecture developed by Digital Equipment Corporation , designed to replace the 32-bit VAX complex instruction set computer ISA and its implementations. Alpha was implemented in microprocessors...
.
MIPS implementations are primarily used in
embedded systemAn embedded system is a computer system designed for specific control functions within a larger system. often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. By contrast, a general-purpose computer, such as a personal...
s such as
Windows CEMicrosoft Windows CE is an operating system developed by Microsoft for embedded systems. Windows CE is a distinct operating system and kernel, rather than a trimmed-down version of desktop Windows...
devices, routers,
residential gatewayA residential gateway is a home networking device, used as a gateway to connect devices in the home to the Internet or other WAN.It is an umbrella term, used to cover multi-function networking computer appliances used in homes, which may combine a DSL or cable modem, a firewall, a consumer-grade...
s, and
video game consoleA video game console is an interactive entertainment computer or customized computer system that produces a video display signal which can be used with a display device to display a video game...
s such as the
Sony, commonly referred to as Sony, is a Japanese multinational conglomerate corporation headquartered in Minato, Tokyo, Japan and the world's fifth largest media conglomerate measured by revenues....
PlayStation 2The PlayStation 2 is a sixth-generation video game console manufactured by Sony as part of the PlayStation series. Its development was announced in March 1999 and it was first released on March 4, 2000, in Japan...
and
PlayStation PortableThe is a handheld game console manufactured and marketed by Sony Corporation Development of the console was announced during E3 2003, and it was unveiled on , 2004, at a Sony press conference before E3 2004...
. Until late 2006, they were also used in many of
SGISilicon Graphics, Inc. was a manufacturer of high-performance computing solutions, including computer hardware and software, founded in 1981 by Jim Clark...
's computer products. MIPS implementations were also used by
Digital Equipment CorporationDigital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
,
NEC, a Japanese multinational IT company, has its headquarters in Minato, Tokyo, Japan. NEC, part of the Sumitomo Group, provides information technology and network solutions to business enterprises, communications services providers and government....
,
Pyramid TechnologyPyramid Technology Corporation was a computer company that produced a number of RISC-based minicomputers at the upper end of the performance range. They also became the second company to ship a multiprocessor Unix system , in 1985, which formed the basis of their product line into the early 1990s...
, Siemens Nixdorf,
Tandem ComputersTandem Computers, Inc. was the dominant manufacturer of fault-tolerant computer systems for ATM networks, banks, stock exchanges, telephone switching centers, and other similar commercial transaction processing applications requiring maximum uptime and zero data loss. The company was founded in...
and others during the late 1980s and 1990s. In the mid to late 1990s, it was estimated that one in three RISC microprocessors produced were MIPS implementations.
RISC pioneer
In 1981, a team led by Junaid Malik, Umair Aftab, Muzaffar Shikari and
John L. HennessyJohn LeRoy Hennessy is an American computer scientist and academician. Hennessy is one of the founders of MIPS Computer Systems Inc. and is the 10th President of Stanford University.-Background:...
at
Stanford UniversityThe Leland Stanford Junior University, commonly referred to as Stanford University or Stanford, is a private research university on an campus located near Palo Alto, California. It is situated in the northwestern Santa Clara Valley on the San Francisco Peninsula, approximately northwest of San...
started work on what would become the first MIPS processor. The basic concept was to increase performance through the use of deep
instruction pipelineAn instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
s. Pipelining as a basic technique was well known before (see
IBM 801The 801 was an experimental minicomputer designed by IBM. The resulting architecture was used in various roles in IBM until the 1980s. The 801 was started as a pure research project led by John Cocke in October 1975 at the Thomas J. Watson Research Center. The name 801 comes from the building the...
for instance), but not developed into its full potential. CPUs are built up from a number of dedicated sub-units such as instruction decoders, ALUs (integer arithmetics and logic), load/store units (handling memory), and so on. In a traditional non-optimized design, a particular instruction in a program sequence must be (almost) completed before the next can be issued for execution; in a pipelined architecture, successive instructions can instead overlap in execution. For instance, at the same time a math instruction is fed into the floating point unit, the load/store unit can fetch the next instruction.
One major barrier to pipelining was that some instructions, like division, take longer to complete and the CPU therefore has to wait before passing the next instruction into the pipeline. One solution to this problem is to use a series of interlocks that allows stages to indicate that they are busy, pausing the other stages upstream. Hennessy's team viewed these interlocks as a major performance barrier since they had to communicate to all the modules in the CPU which takes time, and appeared to limit the clock speed. A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.
Although this design eliminated a number of useful instructions such as multiply and divide it was felt that the overall performance of the system would be dramatically improved because the chips could run at much higher clock rates. This ramping of the speed would be difficult with interlocking involved, as the time needed to set up locks is as much a function of die size as clock rate. The elimination of these instructions became a contentious point.
The other difference between the MIPS design and the competing Berkeley RISC involved the handling of
subroutineIn computer science, a subroutine is a portion of code within a larger program that performs a specific task and is relatively independent of the remaining code....
calls. RISC used a technique called
register windowIn computer engineering, the use of register windows is a technique to improve the performance of a particularly common operation, the procedure call...
s to improve performance of these very common tasks, but this limited the maximum depth of multi-level calls. Each subroutine call required its own set of registers, which in turn required more real estate on the CPU and more complexity in its design. Hennessy felt that a careful compiler could find free registers without resorting to a hardware implementation, and that simply increasing the number of registers would not only make this simple, but increase the performance of all tasks.
In other ways the MIPS design was very much a typical RISC design. To save bits in the instruction word, RISC designs reduce the number of instructions to encode. The MIPS design uses 6 bits of the 32-bit word for the basic opcode; the rest may contain a single 26-bit jump address or it may have up to four 5-bit fields specifying up to three registers plus a shift value combined with another 6-bits of opcode; another format, among several, specifies two registers combined with a 16-bit immediate value, etc. This allowed this CPU to load up the instruction and the data it needed in a single cycle, whereas an (older) non-RISC design, such as the
MOS Technology 6502The MOS Technology 6502 is an 8-bit microprocessor that was designed by Chuck Peddle and Bill Mensch for MOS Technology in 1975. When it was introduced, it was the least expensive full-featured microprocessor on the market by a considerable margin, costing less than one-sixth the price of...
for instance, required separate cycles to load the opcode and the data. This was one of the major performance improvements that RISC offered. However, modern non-RISC designs achieve this speed by other means (such as queues in the CPU).
First hardware
In 1984 Hennessy was convinced of the future commercial potential of the design, and left Stanford to form MIPS Computer Systems. They released their first design, the
R2000The R2000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture . Introduced in January 1986, it was the first commercial implementation of the MIPS architecture and the first merchant RISC processor available to all companies...
, in 1985, improving the design as the
R3000The R3000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture . Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor...
in 1988. These 32-bit CPUs formed the basis of their company through the 1980s, used primarily in
SGISilicon Graphics, Inc. was a manufacturer of high-performance computing solutions, including computer hardware and software, founded in 1981 by Jim Clark...
's series of
workstationA workstation is a high-end microcomputer designed for technical or scientific applications. Intended primarily to be used by one person at a time, they are commonly connected to a local area network and run multi-user operating systems...
s and later
Digital Equipment CorporationDigital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
DECstation workstations and servers. The SGI commercial designs deviated from the Stanford academic research by implementing most of the interlocks in hardware, supplying full multiply and divide instructions (among others). The designs were guided, in part, by software architect Earl Killian who designed the MIPS III 64-bit instruction-set extension, and led the work on the R4000 microarchitecture.
In 1991 MIPS released the first 64-bit microprocessor, the
R4000The R4000 is a microprocessor developed by MIPS Computer Systems that implemented the MIPS III instruction set architecture . Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation...
. The R4000 has an advanced
TLBA translation lookaside buffer is a CPU cache that memory management hardware uses to improve virtual address translation speed. All current desktop and server processors use a TLB to map virtual and physical address spaces, and it is ubiquitous in any hardware which utilizes virtual memory.The...
where the entry contains not just virtual address but also the virtual address space id. Such buffer eliminates the major performance problems from
microkernelIn computer science, a microkernel is the near-minimum amount of software that can provide the mechanisms needed to implement an operating system . These mechanisms include low-level address space management, thread management, and inter-process communication...
s that are slow on competing architectures (Pentium, PowerPC, Alpha) because of the need to flush the TLB on the frequent context switches. However, MIPS had financial difficulties while bringing it to market. The design was so important to SGI, at the time one of MIPS' few major customers, that SGI bought the company outright in 1992 in order to guarantee the design would not be lost. As a subsidiary of SGI, the company became known as
MIPS TechnologiesMIPS Technologies, Inc. , formerly MIPS Computer Systems, Inc., is most widely known for developing the MIPS architecture and a series of pioneering RISC chips. MIPS provides processor architectures and cores for digital home, networking and mobile applications.MIPS Computer Systems Inc. was...
.
Licensable architecture
In the early 1990s MIPS started licensing their designs to third-party vendors. This proved fairly successful due to the simplicity of the core, which allowed it to be used in a number of applications that would have formerly used much less capable
CISCA complex instruction set computer , is a computer where single instructions can execute several low-level operations and/or are capable of multi-step operations or addressing modes within single instructions...
designs of similar
gate countIn microprocessor design, gate count refers to the number of gates build with transistor and other electronic devices, that are needed to implement a design. Even with today's process technology providing what was formerly considered impossible numbers of gates on a single chip, gate counts remain...
and price—the two are strongly related; the price of a CPU is generally related to the number of gates and the number of external pins.
Sun MicrosystemsSun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...
attempted to enjoy similar success by licensing their
SPARCSPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....
core but was not nearly as successful. By the late 1990s MIPS was a powerhouse in the embedded processor field, and in 1997 the 48-millionth MIPS-based CPU shipped, making it the first RISC CPU to outship the famous
68kThe Motorola 680x0/m68000/68000 is a family of 32-bit CISC microprocessors. During the 1980s and early 1990s, they were popular in personal computers and workstations and were the primary competitors of Intel's x86 microprocessors...
family. MIPS was so successful that SGI spun off MIPS Technologies in 1998. Fully half of MIPS' income today comes from licensing their designs, while much of the rest comes from contract design work on cores that will then be produced by third parties.
In 1999 MIPS formalized their licensing system around two basic designs, the 32-bit
MIPS32 (based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V) and the 64-bit
MIPS64 (based on MIPS V). NEC,
Toshibais a multinational electronics and electrical equipment corporation headquartered in Tokyo, Japan. It is a diversified manufacturer and marketer of electrical products, spanning information & communications equipment and systems, Internet-based solutions and services, electronic components and...
and SiByte (later acquired by
BroadcomBroadcom Corporation is a fabless semiconductor company in the wireless and broadband communication business. The company is headquartered in Irvine, California, USA. Broadcom was founded by a professor-student pair Henry Samueli and Henry T. Nicholas III from the University of California, Los...
) each obtained licenses for the MIPS64 as soon as it was announced.
PhilipsKoninklijke Philips Electronics N.V. , more commonly known as Philips, is a multinational Dutch electronics company....
,
LSI LogicLSI Corporation is an electronics company based in Milpitas, California that designs semiconductors and software that accelerate storage and networking in datacenters and mobile networks.-History:...
and
IDTIntegrated Device Technology, Inc. is a publicly traded corporation headquartered in San Jose, California, that designs, manufactures, and markets low-power, high-performance mixed-signal semiconductor solutions for the advanced communications, computing, and consumer industries. The company...
have since joined them. Success followed success, and today the MIPS cores are one of the most-used "heavyweight" cores in the marketplace for computer-like devices (hand-held computers,
set-top boxA set-top box or set-top unit is an information appliance device that generally contains a tuner and connects to a television set and an external source of signal, turning the signal into content which is then displayed on the television screen or other display device.-History:Before the...
es, etc.).
Since the MIPS architecture is licensable, it has attracted several processor
start-upA startup company or startup is a company with a limited operating history. These companies, generally newly created, are in a phase of development and research for markets...
companies over the years. One of the first start-ups to design MIPS processors was
Quantum Effect DevicesQuantum Effect Devices was a company originally named Quantum Effect Design, incorporated in 1991. The three founders, Tom Riordan, Earl Killian and Ray Kunita, were senior managers at MIPS Computer Systems Inc....
(see next section). The MIPS design team that designed the
R4300i started the company SandCraft, which designed the
R5432 for NEC and later produced the
SR71000, one of the first
out-of-order executionIn computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...
processors for the embedded market. The original
DECDigital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
StrongARMThe StrongARM is a family of microprocessors that implemented the ARM V4 instruction set architecture . It was developed by Digital Equipment Corporation and later sold to Intel, who continued to manufacture it before replacing it with the XScale....
team eventually split into two MIPS-based start-ups: SiByte which produced the
SB-1250, one of the first high-performance MIPS-based
systems-on-a-chipA system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
(SOC); while Alchemy Semiconductor (later acquired by AMD) produced the
Au-1000 SoCA system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
for low-power applications.
LexraLexra was a semiconductor intellectual property core company based in Waltham, Massachusetts. It was founded in 1997 and began developing and licensing semiconductor intellectual property cores that implemented the MIPS-I instruction set, except for the four unaligned load and store ...
used a MIPS-
like architecture and added DSP extensions for the audio chip market and multithreading support for the networking market. Due to Lexra not licensing the architecture, two lawsuits were started between the two companies. The first was quickly resolved when Lexra promised not to advertise their processors as MIPS-compatible. The second (about MIPS patent 4814976 for handling unaligned memory access) was protracted, hurt both companies' business, and culminated in MIPS Technologies giving Lexra a free license and a large cash payment.
Two companies have emerged that specialize in building
multi-coreA multi-core processor is a single computing component with two or more independent actual processors , which are the units that read and execute program instructions...
devices using the MIPS architecture.
Raza Microelectronics, Inc.RMI Corporation, also known as RMI, formerly known as Raza Microelectronics, Inc., is a privately held Fabless semiconductor company headquartered in Cupertino, California, which specializes in designing System-on-a-chip processors for networking and consumer media applications.- History :RMI was...
purchased the product line from failing SandCraft and later produced devices that contained eight cores that were targeted at the telecommunications and networking markets. Cavium, originally a security processor vendor also produced devices with eight CPU cores, and later up to 32 cores, for the same markets. Both of these companies designed their cores in-house, just licensing the architecture instead of purchasing cores from MIPS.
The desktop
Among the manufacturers which have made computer
workstationA workstation is a high-end microcomputer designed for technical or scientific applications. Intended primarily to be used by one person at a time, they are commonly connected to a local area network and run multi-user operating systems...
systems using MIPS processors are
SGISilicon Graphics, Inc. was a manufacturer of high-performance computing solutions, including computer hardware and software, founded in 1981 by Jim Clark...
, MIPS Computer Systems, Inc., Whitechapel Workstations,
OlivettiOlivetti S.p.A. is an Italian manufacturer of computers, printers and other business machines.- Founding :The company was founded as a typewriter manufacturer in 1908 in Ivrea, near Turin, by Camillo Olivetti. The firm was mainly developed by his son Adriano Olivetti...
,
Siemens-NixdorfSiemens Nixdorf Informationssysteme, AG was formed in 1990 by the merger of Nixdorf Computer AG and the Siemens' Data Information Services division...
,
AcerAcer Incorporated is a multinational information technology and electronics corporation headquartered in Xizhi, New Taipei City, Taiwan. Acer's products include desktop and laptop PCs, tablet computers, servers, storage devices, displays, smartphones and peripherals...
,
Digital Equipment CorporationDigital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
, NEC, and DeskStation.
Operating systemAn operating system is a set of programs that manage computer hardware resources and provide common services for application software. The operating system is the most important type of system software in a computer system...
s ported to the architecture include SGI's
IRIXIRIX is a computer operating system developed by Silicon Graphics, Inc. to run natively on their 32- and 64-bit MIPS architecture workstations and servers. It was based on UNIX System V with BSD extensions. IRIX was the first operating system to include the XFS file system.The last major version...
,
MicrosoftMicrosoft Corporation is an American public multinational corporation headquartered in Redmond, Washington, USA that develops, manufactures, licenses, and supports a wide range of products and services predominantly related to computing through its various product divisions...
's
Windows NTWindows NT is a family of operating systems produced by Microsoft, the first version of which was released in July 1993. It was a powerful high-level-language-based, processor-independent, multiprocessing, multiuser operating system with features comparable to Unix. It was intended to complement...
(until v4.0),
Windows CEMicrosoft Windows CE is an operating system developed by Microsoft for embedded systems. Windows CE is a distinct operating system and kernel, rather than a trimmed-down version of desktop Windows...
,
LinuxLinux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
, BSD,
UNIXUnix is a multitasking, multi-user computer operating system originally developed in 1969 by a group of AT&T employees at Bell Labs, including Ken Thompson, Dennis Ritchie, Brian Kernighan, Douglas McIlroy, and Joe Ossanna...
System V,
SINIXSINIX was a variant of the Unix operating system from Siemens Nixdorf Informationssysteme. Supersedes SIRM OS and Pyramid Technology's DC/OSx. Its last release under the SINIX name was version 5.43 in 1995...
,
QNXQNX is a commercial Unix-like real-time operating system, aimed primarily at the embedded systems market. The product was originally developed by Canadian company, QNX Software Systems, which was later acquired by Canadian BlackBerry-producer Research In Motion.-Description:As a microkernel-based...
, and MIPS Computer Systems' own
RISC/osRISC/os was a UNIX operating system developed by MIPS Computer Systems, Inc. from 1985 to 1992 for their computer workstations and servers, such as the MIPS M/120 server or MIPS Magnum workstation. It was also known as UMIPS or MIPS OS....
.
There was speculation in the early 1990s that MIPS and other powerful RISC processors would overtake the Intel IA32 architecture. This was encouraged by the support of the first two versions of
MicrosoftMicrosoft Corporation is an American public multinational corporation headquartered in Redmond, Washington, USA that develops, manufactures, licenses, and supports a wide range of products and services predominantly related to computing through its various product divisions...
's
Windows NTWindows NT is a family of operating systems produced by Microsoft, the first version of which was released in July 1993. It was a powerful high-level-language-based, processor-independent, multiprocessing, multiuser operating system with features comparable to Unix. It was intended to complement...
for
AlphaAlpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer instruction set architecture developed by Digital Equipment Corporation , designed to replace the 32-bit VAX complex instruction set computer ISA and its implementations. Alpha was implemented in microprocessors...
, MIPS and
PowerPCPowerPC is a RISC architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM...
- and to a lesser extent the
Clipper architectureThe Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. The architecture never enjoyed much market success, and the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware...
and
SPARCSPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....
. However, as Intel quickly released faster versions of their Pentium class CPUs, Microsoft
Windows NTWindows NT is a family of operating systems produced by Microsoft, the first version of which was released in July 1993. It was a powerful high-level-language-based, processor-independent, multiprocessing, multiuser operating system with features comparable to Unix. It was intended to complement...
v4.0 dropped support for anything but Intel and Alpha. With SGI's decision to transition to the
ItaniumItanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel markets the processors for enterprise servers and high-performance computing systems...
and IA32 architectures, use of MIPS processors on the desktop has now disappeared almost completely.
Embedded markets
Through the 1990s, the MIPS architecture was widely adopted by the embedded market, including for use in
computer networkA computer network, often simply referred to as a network, is a collection of hardware components and computers interconnected by communication channels that allow sharing of resources and information....
ing, telecommunications, video arcade games,
video game consoleA video game console is an interactive entertainment computer or customized computer system that produces a video display signal which can be used with a display device to display a video game...
s,
computer printerIn computing, a printer is a peripheral which produces a text or graphics of documents stored in electronic form, usually on physical print media such as paper or transparencies. Many printers are primarily used as local peripherals, and are attached by a printer cable or, in most new printers, a...
s, digital
set-top boxA set-top box or set-top unit is an information appliance device that generally contains a tuner and connects to a television set and an external source of signal, turning the signal into content which is then displayed on the television screen or other display device.-History:Before the...
es,
digital televisionDigital television is the transmission of audio and video by digital signals, in contrast to the analog signals used by analog TV...
s, DSL and
cable modemA cable modem is a type of network bridge and modem that provides bi-directional data communication via radio frequency channels on a HFC and RFoG infrastructure. Cable modems are primarily used to deliver broadband Internet access in the form of cable Internet, taking advantage of the high...
s, and
personal digital assistantA personal digital assistant , also known as a palmtop computer, or personal data assistant, is a mobile device that functions as a personal information manager. Current PDAs often have the ability to connect to the Internet...
s.
The low power-consumption and heat characteristics of embedded MIPS implementations, the wide availability of embedded development tools, and knowledge about the architecture means use of MIPS microprocessors in embedded roles is likely to remain common.
Synthesizeable cores for embedded markets
In recent years most of the technology used in the various MIPS generations has been offered as
IP-coresIn electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or chip layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone...
(building-blocks) for embedded processor designs. Both
32-bitThe range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
and
64-bit64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...
basic cores are offered, known as the
4K and
5K. These cores can be mixed with add-in units such as FPUs,
SIMDSingle instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...
systems, various input/output devices, etc.
MIPS cores have been commercially successful, now being used in many consumer and industrial applications. MIPS cores can be found in newer
CiscoCisco may refer to:Companies:*Cisco Systems, a computer networking company* Certis CISCO, corporatised entity of the former Commercial and Industrial Security Corporation in Singapore...
,
LinksysLinksys by Cisco, commonly known as Linksys, is a brand of home and small office networking products now produced by Cisco Systems, though once a separate company founded in 1995 before being acquired by Cisco in 2003...
and
Mikrotik's routerboardMikrotīkls Ltd., known internationally as MikroTik, is a Latvian manufacturer of computer networking equipment. It sells wireless products and routers. The company was founded in 1995, with the intent to sell in the emerging wireless technology market. As of 2007, the company had more than 70...
routers,
cable modemA cable modem is a type of network bridge and modem that provides bi-directional data communication via radio frequency channels on a HFC and RFoG infrastructure. Cable modems are primarily used to deliver broadband Internet access in the form of cable Internet, taking advantage of the high...
s and
ADSLAsymmetric digital subscriber line is a type of digital subscriber line technology, a data communications technology that enables faster data transmission over copper telephone lines than a conventional voiceband modem can provide. It does this by utilizing frequencies that are not used by a voice...
modems, smartcards,
laser printerA laser printer is a common type of computer printer that rapidly produces high quality text and graphics on plain paper. As with digital photocopiers and multifunction printers , laser printers employ a xerographic printing process, but differ from analog photocopiers in that the image is produced...
engines,
set-top boxA set-top box or set-top unit is an information appliance device that generally contains a tuner and connects to a television set and an external source of signal, turning the signal into content which is then displayed on the television screen or other display device.-History:Before the...
es,
robotA robot is a mechanical or virtual intelligent agent that can perform tasks automatically or with guidance, typically by remote control. In practice a robot is usually an electro-mechanical machine that is guided by computer and electronic programming. Robots can be autonomous, semi-autonomous or...
s, handheld computers, Sony
PlayStation 2The PlayStation 2 is a sixth-generation video game console manufactured by Sony as part of the PlayStation series. Its development was announced in March 1999 and it was first released on March 4, 2000, in Japan...
and Sony
PlayStation PortableThe is a handheld game console manufactured and marketed by Sony Corporation Development of the console was announced during E3 2003, and it was unveiled on , 2004, at a Sony press conference before E3 2004...
. In cellphone/PDA applications, MIPS has been largely unable to displace the incumbent, competing
ARM architectureARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
.
MIPS architecture processors include: IDT RC32438;
ATIAs a word, Ati may refer to:* Ati, a town in Chad* Ati, a Negrito ethnic group in the Philippines* Ati-Atihan Festival, an annual celebration held in the Philippines* Ati, a queen of the fabled Land of Punt in Africa...
Xilleon; Alchemy Au1000, 1100, 1200; Broadcom Sentry5;
RMIRMI Corporation, also known as RMI, formerly known as Raza Microelectronics, Inc., is a privately held Fabless semiconductor company headquartered in Cupertino, California, which specializes in designing System-on-a-chip processors for networking and consumer media applications.- History :RMI was...
XLR7xx,
CaviumCavium is a San Jose, California-based company specializing in ARM-based and MIPS-based network, video and security processors. Cavium offers processor and board level products targeting routers, switches, appliances, storage and servers.-Major acquisitions::...
Octeon CN30xx, CN31xx, CN36xx, CN38xx and CN5xxx;
Infineon TechnologiesInfineon Technologies AG is a German semiconductor manufacturer and was founded on April 1, 1999, when the semiconductor operations of the parent company Siemens AG were spun off to form a separate legal entity. , Infineon has 25,149 employees worldwide...
EasyPort, Amazon, Danube, ADM5120, WildPass, INCA-IP, INCA-IP2;
Microchip TechnologyMicrochip Technology is an American manufacturer of microcontroller, memory and analog semiconductors. Its products include microcontrollers , Serial EEPROM devices, Serial SRAM devices, KEELOQ devices, radio frequency devices, thermal, power and battery management analog devices, as well as...
PIC32;
NEC, a Japanese multinational IT company, has its headquarters in Minato, Tokyo, Japan. NEC, part of the Sumitomo Group, provides information technology and network solutions to business enterprises, communications services providers and government....
EMMA and EMMA2, NEC VR4181A, VR4121, VR4122, VR4181A, VR5432, VR5500; Oak Technologies Generation;
PMC-SierraPMC-Sierra is a fabless semiconductor company which develops and sells devices into the communications, storage, printing, and embedded computing marketplaces.-Corporate history:...
RM11200;
QuickLogicQuickLogic Corporation is a manufacturer of Customer Specific Standard Products, or CSSP.Until 2007 they were a supplier of Field-Programmable Gate Arrays based on antifuse technology, making the devices one-time programmable...
QuickMIPS ESP; Toshiba
Donau,
Toshibais a multinational electronics and electrical equipment corporation headquartered in Tokyo, Japan. It is a diversified manufacturer and marketer of electrical products, spanning information & communications equipment and systems, Internet-based solutions and services, electronic components and...
TMPR492x, TX4925, TX9956, TX7901.
MIPS-based supercomputers
One of the more interesting applications of the MIPS architecture is its use in massive processor count supercomputers.
Silicon GraphicsSilicon Graphics, Inc. was a manufacturer of high-performance computing solutions, including computer hardware and software, founded in 1981 by Jim Clark...
(SGI) refocused its business from desktop graphics workstations to the
high-performance computingHigh-performance computing uses supercomputers and computer clusters to solve advanced computation problems. Today, computer systems approaching the teraflops-region are counted as HPC-computers.-Overview:...
market in the early 1990s. The success of the company's first foray into server systems, the
ChallengeThe Challenge, code-named Eveready and Terminator , is a family of server computers and supercomputers developed and manufactured by Silicon Graphics in the early to mid-1990s that succeeded the earlier Power series systems...
series based on the R4400 and
R8000The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. , Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.-History:Development of the...
, and later
R10000The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture developed by MIPS Technologies, Inc. , then a division of Silicon Graphics, Inc. . The chief designers were Chris Rowen and Kenneth C. Yeager...
, motivated SGI to create a vastly more powerful system. The introduction of the integrated R10000 allowed SGI to produce a system, the Origin 2000, eventually scalable to 1024 CPUs using its
NUMAlinkNUMAlink is a system interconnect developed by SGI for use in its distributed shared memory ccNUMA computer systems. NUMAlink was originally developed by SGI for their Origin 2000 and Onyx2 systems...
cc-NUMA interconnect. The Origin 2000 begat the Origin 3000 series which topped out with the same 1024 maximum CPU count but using the R14000 and R16000 chips up to 700 MHz. Its MIPS based supercomputers were withdrawn in 2005 when SGI made the strategic decision to move to Intel's IA-64 architecture.
A high-performance computing startup called
SiCortexSiCortex is a supercomputer manufacturer founded in 2003 and headquartered in Maynard, Massachusetts. On 27 May 2009, HPCwire reported that the company had shut down its operations, laid off most of its staff, and is seeking a buyer for its assets. The Register reported that Gerbsman Partners was...
, Inc. introduced a massively parallel MIPS based supercomputer in 2007. The machines are based on the MIPS64 architecture and a high performance interconnect using a
Kautz graph topology. The system is very power efficient and computationally powerful. The most unique aspect of the system is its multicore processing node which integrates six MIPS64 cores, a
crossbar- Structural engineering :* A primitive latch consisting of a post barring a door* The top tube of a bicycle frame* The horizontal member of many sports goals including those for hockey, association football, rugby league, rugby union and American football...
memory controllerThe memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
, interconnect DMA engine, Gigabit Ethernet and PCI Express controllers all on a single chip which consumes only 10 watts of power, yet has a peak floating point performance of 6 GFLOPs. The most powerful configuration, the SC5832, is a single cabinet supercomputer consisting of 972 such node chips for a total of 5832 MIPS64 processor cores and 8.2 teraFLOPS of peak performance.
Loongson
Loongson is a MIPS-compatible family of microprocessors designed by the
Chinese Academy of SciencesThe Chinese Academy of Sciences , formerly known as Academia Sinica, is the national academy for the natural sciences of the People's Republic of China. It is an institution of the State Council of China. It is headquartered in Beijing, with institutes all over the People's Republic of China...
. The internal microarchitecture of Loongson microprocessors was designed independently by the Chinese, and early implementations of the family lacked four instructions patented by MIPS Technologies. In June 2009, ICT licenced the MIPS32 and MIPS64 architectures directly from MIPS Technologies.
Starting from 2006, a number of companies released Loongson-based computers, including
nettopNettop may refer to:*Nettop, a type of computer*NetTop, a NSA project...
s and
netbookNetbooks are a category of small, lightweight, legacy-free, and inexpensive laptop computers.At their inception in late 2007 as smaller notebooks optimized for low weight and low cost — netbooks omitted certain features , featured smaller screens and keyboards, and offered reduced computing...
s designed for low-power use.
Dawning 6000
The high-performance Dawning 6000, which has a projected speed of over one quadrillion operations per second, will incorporate the Loongson processor as its core. Dawning 6000 is currently jointly developed by the Institute of Computing Technology under the Chinese Academy of Sciences and the Dawning Information Industry Company. Li Guojie, chairman of Dawning Information Industry Company and director and academician of the Institute of Computing Technology, said research and development of the Dawning 6000 is expected to be completed in two years. By then, Chinese-made high-performance computers will be expected to achieve two major breakthroughs: first, the adoption of domestic-made central processing units (CPUs); second, the existing cluster-based system structure of high-performance computers will be changed once the computing speed reaches one quadrillion operations per second.
MIPS IV
MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS. The first implementation of MIPS IV was the
R8000The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. , Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.-History:Development of the...
, which was introduced in 1994. MIPS IV added:
- Register + register addressing for floating point loads and stores
- Single- and double-precision floating point fused-multiply adds and subtracts
- Conditional move instructions for both integer and floating-point
- Extra condition bits in the floating point control and status register, bringing the total to eight
MIPS V
MIPS V is the fifth version of the architecture, announced on 21 October 1996 at the Microprocessor Forum 1996. MIPS V was designed to improve the performance of 3D graphics applications. In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from SGI. MIPS V was complemented by the integer-only
MIPS Digital Media ExtensionsThe MDMX , also known as MaDMaX, is an extension to the MIPS instruction set architecture released in October 1996 at the Microprocessor Forum.- History :...
(MDMX) multimedia extensions, which were announced on the same date as MIPS V.
MIPS V implementations were never introduced. In 1997, SGI announced the "H1" or "Beast" and the "H2" or "Capitan" microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in 1999. The "H1" and "H2" projects were later combined and were eventually canceled in 1998.
MIPS V added a new data type, the pair-single (PS), which consisted of two single-precision (32-bit) floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data. It was the first architecture to exploit floating-point SIMD with existing resources.
CPU family
The first commercial MIPS model, the
R2000The R2000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture . Introduced in January 1986, it was the first commercial implementation of the MIPS architecture and the first merchant RISC processor available to all companies...
, was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the register file; these result-retrieving instructions were interlocked.
The R2000 could be booted either big-endian or little-endian. It had thirty-two 32-bit general purpose registers, but no condition code register (the designers considered it a potential bottleneck), a feature it shares with the AMD 29000 and the
AlphaAlpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer instruction set architecture developed by Digital Equipment Corporation , designed to replace the 32-bit VAX complex instruction set computer ISA and its implementations. Alpha was implemented in microprocessors...
. Unlike other registers, the
program counterThe program counter , commonly called the instruction pointer in Intel x86 microprocessors, and sometimes called the instruction address register, or just part of the instruction sequencer in some computers, is a processor register that indicates where the computer is in its instruction sequence...
is not directly accessible.
The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional
R2010 FPUA floating-point unit is a part of a computer system specially designed to carry out operations on floating point numbers. Typical operations are addition, subtraction, multiplication, division, and square root...
, which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision.
The
R3000The R3000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture . Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor...
succeeded the R2000 in 1988, adding 32 KB (soon increased to 64 KB) caches for instructions and data, along with
cache coherencyIn computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...
support for multiprocessor use. While there were flaws in the R3000's multiprocessor support, it still managed to be a part of several successful multiprocessor designs. The R3000 also included a built-in
MMUA memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...
, a common feature on CPUs of the era. The R3000, like the R2000, could be paired with a
R3010 FPU. The R3000 was the first successful MIPS design in the marketplace, and eventually over one million were made. A speed-bumped version of the R3000 running up to 40 MHz, the
R3000A delivered a performance of 32 VUPs (VAX Unit of Performance). The MIPS R3000A-compatible
R3051 running at 33.8688 MHz was the processor used in the
Sony, commonly referred to as Sony, is a Japanese multinational conglomerate corporation headquartered in Minato, Tokyo, Japan and the world's fifth largest media conglomerate measured by revenues....
PlayStationThe is a 32-bit fifth-generation video game console first released by Sony Computer Entertainment in Japan on December 3, .The PlayStation was the first of the PlayStation series of consoles and handheld game devices. The PlayStation 2 was the console's successor in 2000...
. Third-party designs include Performance Semiconductor's
R3400 and IDT's
R3500, both of them were R3000As with an integrated R3010 FPU.
Toshibais a multinational electronics and electrical equipment corporation headquartered in Tokyo, Japan. It is a diversified manufacturer and marketer of electrical products, spanning information & communications equipment and systems, Internet-based solutions and services, electronic components and...
's
R3900 was a virtually first
SoCA system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
for the early
handheld PCA Handheld PC, or H/PC for short, is a term for a computer built around a form factor which is smaller than any standard laptop computer. It is sometimes referred to as a Palmtop. The first handheld device compatible with desktop IBM personal computers of the time was the Atari Portfolio of 1989...
s that ran
Windows CEMicrosoft Windows CE is an operating system developed by Microsoft for embedded systems. Windows CE is a distinct operating system and kernel, rather than a trimmed-down version of desktop Windows...
. A radiation-hardened variant for space applications, the
Mongoose-VThe Mongoose-V 32-bit microprocessor for spacecraft onboard computer applications is a radiation-hardened and expanded 10–15 MHz version of the MIPS R3000 CPU. The Mongoose was developed by Synova, Inc...
, is a R3000 with an integrated R3010 FPU.
The
R4000The R4000 is a microprocessor developed by MIPS Computer Systems that implemented the MIPS III instruction set architecture . Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation...
series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture, moved the FPU onto the main die to create a single-chip microprocessor, and operated at a radically high internal clock speed (it was introduced at 100 MHz). However, in order to achieve the clock speed the caches were reduced to 8 KB each and they took three cycles to access. The high operating frequencies were achieved through the technique of deep pipelining (called super-pipelining at the time). The improved
R4400 followed in 1993. It had larger 16 KB primary caches, largely bug-free 64-bit operation, and support for a larger L2 cache.
MIPS, now a division of SGI called MTI, designed the low-cost
R4200The R4200 is a microprocessor designed by MIPS Technologies, Inc. that implemented the MIPS III instruction set architecture . It was also known as the VRX during development. The microprocessor was licensed to NEC, and the company fabricated and marketed it as the VR4200. The first VR4200, an...
, the basis for the even cheaper
R4300i. A derivative of this microprocessor, the NEC VR4300, was used in the
Nintendo 64The , often referred to as N64, was Nintendo′s third home video game console for the international market. Named for its 64-bit CPU, it was released in June 1996 in Japan, September 1996 in North America, March 1997 in Europe and Australia, September 1997 in France and December 1997 in Brazil...
game console.
Quantum Effect DevicesQuantum Effect Devices was a company originally named Quantum Effect Design, incorporated in 1991. The three founders, Tom Riordan, Earl Killian and Ray Kunita, were senior managers at MIPS Computer Systems Inc....
(QED), a separate company started by former MIPS employees, designed the
R4600 Orion, the
R4700 Orion, the
R4650 and the
R5000. Where the R4000 had pushed clock frequency and sacrificed cache capacity, the QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the
SGI IndyThe Indy, code-named "Guinness", is a low-end workstation introduced on 12 July 1993. Developed and manufactured by Silicon Graphics Incorporated , it was the result of their attempt to obtain a share of the low-end computer-aided design market, which was dominated at the time by other workstation...
workstation as well as the first MIPS based Cisco routers, such as the 36x0 and 7x00-series routers. The R4650 was used in the original WebTV set-top boxes (now Microsoft TV). The R5000 FPU had more flexible single precision floating-point scheduling than the R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 in order to emphasize the improvement. QED later designed the
RM7000 and
RM9000 family of devices for embedded markets like networking and laser printers. QED was acquired by the semiconductor manufacturer
PMC-SierraPMC-Sierra is a fabless semiconductor company which develops and sells devices into the communications, storage, printing, and embedded computing marketplaces.-Corporate history:...
in August 2000, the latter company continuing to invest in the MIPS architecture. The
RM7000 included an on-board 256 KB level 2 cache and a controller for optional level three cache. The
RM9xx0 were a family of
SOCA system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
devices which included
northbridgeThe northbridge has historically been one of the two chips in the core logic chipset on a PC motherboard, the other being the southbridge. Increasingly these functions have migrated to the CPU chip itself, beginning with memory and graphics controllers. For Intel Sandy Bridge and AMD Fusion...
peripherals such as
memory controllerThe memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
,
PCIConventional PCI is a computer bus for attaching hardware devices in a computer...
controller,
gigabit ethernetGigabit Ethernet is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second , as defined by the IEEE 802.3-2008 standard. It came into use beginning in 1999, gradually supplanting Fast Ethernet in wired local networks where it performed...
controller and fast IO such as a
hypertransportHyperTransport , formerly known as Lightning Data Transport , is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2, 2001...
port.
The
R8000The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. , Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.-History:Development of the...
(1994) was the first
superscalarA superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate...
MIPS design, able to execute two integer or floating point and two memory instructions per cycle. The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's
POWER ChallengeThe Challenge, code-named Eveready and Terminator , is a family of server computers and supercomputers developed and manufactured by Silicon Graphics in the early to mid-1990s that succeeded the earlier Power series systems...
servers in the mid 1990s and later became available in the POWER Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users, and the R8000 was in the marketplace for only a year and remains fairly rare.
In 1995, the
R10000The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture developed by MIPS Technologies, Inc. , then a division of Silicon Graphics, Inc. . The chief designers were Chris Rowen and Kenneth C. Yeager...
was released. This processor was a single-chip design, ran at a faster clock speed than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.
Later designs have all been based upon R10000 core. The
R12000 used a 0.25 micrometre process to shrink the chip and achieve higher clock rates. The revised
R14000 allowed higher clock rates with additional support for
DDRDouble data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...
SRAMStatic random-access memory is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM , it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit...
in the off-chip
cacheA CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
. Later iterations are named the
R16000 and the
R16000A and feature increased clock speed and smaller die manufacturing compared with before.
Other members of the MIPS family include the
R6000The R6000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS II instruction set architecture . The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II...
, an
ECLIn electronics, emitter-coupled logic , is a logic family that achieves high speed by using an overdriven BJT differential amplifier with single-ended input, whose emitter current is limited to avoid the slow saturation region of transistor operation....
implementation produced by
Bipolar Integrated TechnologyBipolar Integrated Technology was a semiconductor company based in Beaverton, Oregon which sold products implemented with ECL technology. The company was founded in 1983 by former Floating Point Systems, Intel, and Tektronix engineers. The company was later renamed BIT Inc..The initial product...
. The R6000 introduced the MIPS II instruction set. Its
TLBA translation lookaside buffer is a CPU cache that memory management hardware uses to improve virtual address translation speed. All current desktop and server processors use a TLB to map virtual and physical address spaces, and it is ubiquitous in any hardware which utilizes virtual memory.The...
and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from the mainstream market.
MIPS Microprocessors
| Model |
Frequency (MHz) |
Year |
Process (nm) |
Transistors (millions) |
Die Size (mm2) |
Pin Count |
Power (W) |
D. cache (KB) |
I. cache (KB) |
L2 Cache |
L3 Cache |
| R2000 The R2000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture . Introduced in January 1986, it was the first commercial implementation of the MIPS architecture and the first merchant RISC processor available to all companies...
|
8–16.67 |
1985 |
2000 |
0.11 |
? |
? |
? |
? |
32 |
64 |
None |
None |
| R3000 The R3000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture . Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor...
|
12–40 |
1988 |
1200 |
0.11 |
66.12 |
145 |
4 |
? |
64 |
64 |
0–256 KB External |
None |
| R4000 The R4000 is a microprocessor developed by MIPS Computer Systems that implemented the MIPS III instruction set architecture . Officially announced on 1 October 1991, it was one of the first 64-bit microprocessors and the first MIPS III implementation...
|
100 |
1991 |
800 |
1.35 |
213 |
179 |
15 |
5 |
8 |
8 |
1 MB External |
None |
| R4400 |
100–250 |
1992 |
600 |
2.3 |
186 |
179 |
15 |
5 |
16 |
16 |
1-4 MB External |
None |
| R4600 The R4600, code-named "Orion", is a microprocessor developed by Quantum Effect Design that implemented the MIPS III instruction set architecture . As QED was a design firm that did not fabricate or sell their designs, the R4600 was first licensed to Integrated Device Technology , and later to...
|
100–133 |
1994 |
640 |
2.2 |
77 |
179 |
4.6 |
5 |
16 |
16 |
512 KB External |
None |
| R4650 |
133–180 |
1994 |
640 |
2.2? |
77? |
179 |
4.6? |
5 |
16 |
16 |
512 KB External |
None |
| R4700 |
100–200 |
1996 |
500 |
2.2? |
? |
179 |
? |
? |
16 |
16 |
External |
none |
| R5000 The R5000 is a microprocessor that implements the MIPS IV instruction set architecture developed by Quantum Effect Design . The project was funded by MIPS Technologies, Inc , also the licensor. MTI then licensed the design to Integrated Device Technology , NEC, NKK, and Toshiba...
|
150–200 |
1996 |
350 |
3.7 |
84 |
223 |
10 |
3.3 |
32 |
32 |
1 MB External |
None |
| R8000 The R8000 is a microprocessor chipset developed by MIPS Technologies, Inc. , Toshiba, and Weitek. It was the first implementation of the MIPS IV instruction set architecture. The R8000 is also known as the TFP, for Tremendous Floating-Point, its name during development.-History:Development of the...
|
75–90 |
1994 |
700 |
2.6 |
299 |
591+591 |
30 |
3.3 |
16 |
16 |
4 MB External |
None |
| R10000 The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture developed by MIPS Technologies, Inc. , then a division of Silicon Graphics, Inc. . The chief designers were Chris Rowen and Kenneth C. Yeager...
|
150–250 |
1996 |
350, 250 |
6.7 |
299 |
599 |
30 |
3.3 |
32 |
32 |
512 KB–16 MB external |
None |
| R12000 |
270–400 |
1998 |
250, 180 |
6.9 |
204 |
600 |
20 |
4 |
32 |
32 |
512 KB–16 MB external |
None |
| RM7000 |
250–600 |
1998 |
250, 180, 130 |
18 |
91 |
304 |
10, 6, 3 |
3.3, 2.5, 1.5 |
16 |
16 |
256 KB internal |
1 MB external |
| MIPS32 4K |
|
1999 |
|
|
|
|
|
|
|
|
|
|
| MIPS64 5K |
|
1999 |
|
|
|
|
|
|
|
|
|
|
| MIPS64 20K |
|
2000 |
|
|
|
|
|
|
|
|
|
|
| R14000 |
500–600 |
2001 |
130 |
7.2 |
204 |
527 |
17 |
? |
32 |
32 |
512 KB–16 MB external |
None |
| R16000 |
700–1000 |
2002 |
110 |
? |
? |
? |
20 |
? |
32 |
32 |
512 KB–16 MB external |
None |
| MIPS32 24K |
400 (130nm)
750 (65nm)
1468 (40nm) |
2003 |
40–130 |
? |
0.83 |
? |
? |
? |
64 |
64 |
4–16 MB external |
None |
| MIPS32 34K |
500 (90nm)
1454 (40nm) |
2006 |
90, 65, 40 |
|
|
|
|
|
|
|
|
|
| MIPS32 74K |
1080 |
2007 |
65 |
|
|
|
|
|
|
|
|
|
| MIPS32 1004K |
1100 |
2008 |
65 |
|
|
|
|
|
|
|
|
|
| MIPS32 1074K |
1500 |
2010 |
40 |
|
|
|
|
|
|
|
|
|
MIPS I instruction formats
Instructions are divided into three types: R, I and J. Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.
The following are the three formats used for the core instruction set:
| Type |
-31- format (bits) -0- |
| R |
opcode (6) |
rs (5) |
rt (5) |
rd (5) |
shamt (5) |
funct (6) |
| I |
opcode (6) |
rs (5) |
rt (5) |
immediate (16) |
| J |
opcode (6) |
address (26) |
MIPS assembly language
These are assembly language instructions that have direct hardware implementation, as opposed to
pseudoinstructions which are translated into multiple real instructions before being assembled.
- In the following, the register letters d, t, and s are placeholders for (register) numbers or register names.
- C denotes a constant (immediate).
- All the following instructions are native instructions.
- Opcodes and funct codes are in hexadecimal.
- The MIPS32 Instruction Set states that the word unsigned as part of Add and Subtract instructions, is a misnomer. The difference between signed and unsigned versions of commands is not a sign extension (or lack thereof) of the operands, but controls whether a trap is executed on overflow (e.g. Add) or an overflow is ignored (Add unsigned). An immediate operand CONST to these instructions is always sign-extended.
Integer
MIPS has 32 integer registers. Data must be in registers to perform arithmetic. Register $0 always holds 0 and register $1 is normally reserved for the assembler (for handling pseudo instructions and large constants).
The encoding shows which bits correspond to which parts of the instruction. A hyphen (-) is used to indicate don't cares.
| Category | Name | Instruction syntax | Meaning | | Format/opcode/funct | Notes/Encoding |
| Arithmetic |
Add |
add $d,$s,$t |
$d = $s + $t |
R |
0 |
2016 |
adds two registers, executes a trap on overflow
000000ss sssttttt ddddd--- --100000 |
| Add unsigned |
addu $d,$s,$t |
$d = $s + $t |
R |
0 |
2116 |
as above but ignores an overflow
000000ss sssttttt ddddd--- --100001 |
| Subtract |
sub $d,$s,$t |
$d = $s - $t |
R |
0 |
2216 |
subtracts two registers, executes a trap on overflow
000000ss sssttttt ddddd--- --100010 |
| Subtract unsigned |
subu $d,$s,$t |
$d = $s - $t |
R |
0 |
2316 |
as above but ignores an overflow
000000ss sssttttt ddddd000 00100011 |
| Add immediate |
addi $t,$s,C |
$t = $s + C (signed) |
I |
816 |
- |
Used to add sign-extended constants (and also to copy one register to another: addi $1, $2, 0), executes a trap on overflow
001000ss sssttttt CCCCCCCC CCCCCCCC |
| Add immediate unsigned |
addiu $t,$s,C |
$t = $s + C (signed) |
I |
916 |
- |
as above but ignores an overflow
001001ss sssttttt CCCCCCCC CCCCCCCC |
| Multiply |
mult $s,$t |
LO = (($s * $t) << 32) >> 32;
HI = ($s * $t) >> 32; |
R |
0 |
1816 |
Multiplies two registers and puts the 64-bit result in two special memory spots - LO and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) $s * $t . See mfhi and mflo for accessing LO and HI regs. |
| Divide |
div $s, $t |
LO = $s / $t HI = $s % $t |
R |
0 |
1A16 |
Divides two registers and puts the 32-bit integer result in LO and the remainder in HI. |
| Divide unsigned |
divu $s, $t |
LO = $s / $t HI = $s % $t |
R |
0 |
1B16 |
Divides two registers and puts the 32-bit integer result in LO and the remainder in HI. |
| Data Transfer |
Load double word |
ld $t,C($s) |
$t = Memory[$s + C] |
I |
2316 |
- |
loads the word stored from: MEM[$s+C] and the following 7 bytes to $t and the next register. |
| Load word |
lw $t,C($s) |
$t = Memory[$s + C] |
I |
2316 |
- |
loads the word stored from: MEM[$s+C] and the following 3 bytes. |
| Load halfword |
lh $t,C($s) |
$t = Memory[$s + C] (signed) |
I |
2116 |
- |
loads the halfword stored from: MEM[$s+C] and the following byte. Sign is extended to width of register. |
| Load halfword unsigned |
lhu $t,C($s) |
$t = Memory[$s + C] (unsigned) |
I |
2516 |
- |
As above without sign extension Sign extension is the operation, in computer arithmetic, of increasing the number of bits of a binary number while preserving the number's sign and value...
. |
| Load byte |
lb $t,C($s) |
$t = Memory[$s + C] (signed) |
I |
2016 |
- |
loads the byte stored from: MEM[$s+C]. |
| Load byte unsigned |
lbu $t,C($s) |
$t = Memory[$s + C] (unsigned) |
I |
2416 |
- |
As above without sign extension. |
| Store double word |
sd $t,C($s) |
Memory[$s + C] = $t |
I |
|
- |
stores two words from $t and the next register into: MEM[$s+C] and the following 7 bytes. The order of the operands is a large source of confusion. |
| Store word |
sw $t,C($s) |
Memory[$s + C] = $t |
I |
2B16 |
- |
stores a word into: MEM[$s+C] and the following 3 bytes. The order of the operands is a large source of confusion. |
| Store half |
sh $t,C($s) |
Memory[$s + C] = $t |
I |
2916 |
- |
stores the first half of a register (a halfword) into: MEM[$s+C] and the following byte. |
| Store byte |
sb $t,C($s) |
Memory[$s + C] = $t |
I |
2816 |
- |
stores the first fourth of a register (a byte) into: MEM[$s+C]. |
| Load upper immediate |
lui $t,C |
$t = C << 16 |
I |
F16 |
- |
loads a 16-bit immediate operand into the upper 16-bits of the register specified. Maximum value of constant is 216-1 |
| Move from high |
mfhi $d |
$d = HI |
R |
0 |
1016 |
Moves a value from HI to a register. Do not use a multiply or a divide instruction within two instructions of mfhi (that action is undefined because of the MIPS pipeline). |
| Move from low |
mflo $d |
$d = LO |
R |
0 |
1216 |
Moves a value from LO to a register. Do not use a multiply or a divide instruction within two instructions of mflo (that action is undefined because of the MIPS pipeline). |
| Move from Control Register |
mfcZ $t, $s |
$t = Coprocessor[Z].ControlRegister[$s] |
R |
0 |
|
Moves a 4 byte value from Coprocessor Z Control register to a general purpose register. Sign extension. |
| Move to Control Register |
mtcZ $t, $s |
Coprocessor[Z].ControlRegister[$s] = $t |
R |
0 |
|
Moves a 4 byte value from a general purpose register to a Coprocessor Z Control register. Sign extension. |
| Logical |
And |
and $d,$s,$t |
$d = $s & $t |
R |
0 |
2416 |
Bitwise Bitwise may refer to:* Bitwise operation, a basic function in computer programming* Bitwise IIT Kharagpur, an algorithm-intensive programming contest by CSE IIT Kharagpur...
and
000000ss sssttttt ddddd--- --100100 |
| And immediate |
andi $t,$s,C |
$t = $s & C |
I |
C16 |
- |
Leftmost 16 bits are padded with 0's
001100ss sssttttt CCCCCCCC CCCCCCCC |
| Or |
or $d,$s,$t |
$d = $s | $t |
R |
0 |
2516 |
Bitwise Bitwise may refer to:* Bitwise operation, a basic function in computer programming* Bitwise IIT Kharagpur, an algorithm-intensive programming contest by CSE IIT Kharagpur...
or |
| Or immediate |
ori $t,$s,C |
$t = $s | C |
I |
D16 |
- |
Leftmost 16 bits are padded with 0's |
| Exclusive or |
xor $d,$s,$t |
$d = $s ^ $t |
R |
0 |
2616 |
|
| Nor |
nor $d,$s,$t |
$d = ~ ($s | $t) |
R |
0 |
2716 |
Bitwise Bitwise may refer to:* Bitwise operation, a basic function in computer programming* Bitwise IIT Kharagpur, an algorithm-intensive programming contest by CSE IIT Kharagpur...
nor |
| Set on less than |
slt $d,$s,$t |
$d = ($s < $t) |
R |
0 |
2A16 |
Tests if one register is less than another. |
| Set on less than immediate |
slti $t,$s,C |
$t = ($s < C) |
I |
A16 |
- |
Tests if one register is less than a constant. |
| Bitwise Shift |
Shift left logical |
sll $d,$t,shamt |
$d = $t << shamt |
R |
0 |
0 |
shifts shamt number of bits to the left (multiplies by  ) |
| Shift right logical |
srl $d,$t,shamt |
$d = $t >> shamt |
R |
0 |
216 |
shifts shamt number of bits to the right - zeros are shifted in (divides by  ). Note that this instruction only works as division of a two's complement number if the value is positive. |
| Shift right arithmetic |
sra $d,$t,shamt |
 |
R |
0 |
316 |
shifts shamt number of bits - the sign bit is shifted in (divides 2's complement number by  ) |
| Conditional branch |
Branch on equal |
beq $s,$t,C |
if ($s $t) go to PC+4+4*C |
I |
416 |
- |
Goes to the instruction at the specified address if two registers are equal.
000100ss sssttttt CCCCCCCC CCCCCCCC |
| Branch on not equal |
bne $s,$t,C |
if ($s != $t) go to PC+4+4*C |
I |
516 |
- |
Goes to the instruction at the specified address if two registers are not equal. |
| Unconditional jump |
Jump |
j C |
PC = PC+4[31:28] . C*4 |
J |
216 |
- |
Unconditionally jumps to the instruction at the specified address. |
| Jump register |
jr $s |
goto address $s |
R |
0 |
816 |
Jumps to the address contained in the specified register |
| Jump and link |
jal C |
$31 = PC + 8; PC = PC+4[31:28] . C*4 |
J |
316 |
- |
For procedure call - used to call a subroutine, $31 holds the return address; returning from a subroutine is done by: jr $31. Return address is PC + 8, not PC + 4 due to the use of a branch delay slot which forces the instruction after the jump to be executed |
Note: In MIPS assembly code, the offset for branching instructions can be represented by a label elsewhere in the code.
Note: There is no corresponding
load lower immediate instruction; this can be done by using addi (add immediate, see below) or ori (or immediate) with the register $0 (whose value is always zero). For example, both
addi $1, $0, 100 and
ori $1, $0, 100 load the decimal value 100 into register $1.
Note: Subtracting an immediate can be done with adding the negation of that value as the immediate.
Floating point
MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair.
| Category | Name | Instruction syntax | Meaning | | Format/opcode/funct | Notes/Encoding |
| Arithmetic |
FP add single |
add.s $x,$y,$z |
$x = $y + $z |
|
|
|
Floating-Point add (single precision) |
| FP subtract single |
sub.s $x,$y,$z |
$x = $y - $z |
|
|
|
Floating-Point subtract (single precision) |
| FP multiply single |
mul.s $x,$y,$z |
$x = $y * $z |
|
|
|
Floating-Point multiply (single precision) |
| FP divide single |
div.s $x,$y,$z |
$x = $y / $z |
|
|
|
Floating-Point divide (single precision) |
| FP add double |
add.d $x,$y,$z |
$x = $y + $z |
|
|
|
Floating-Point add (double precision) |
| FP subtract double |
sub.d $x,$y,$z |
$x = $y - $z |
|
|
|
Floating-Point subtract (double precision) |
| FP multiply double |
mul.d $x,$y,$z |
$x = $y * $z |
|
|
|
Floating-Point multiply (double precision) |
| FP divide double |
div.d $x,$y,$z |
$x = $y / $z |
|
|
|
Floating-Point divide (double precision) |
| Data Transfer |
Load word coprocessor |
lwcZ $x,CONST ($y) |
Coprocessor[Z].DataRegister[$x] = Memory[$y + CONST] |
I |
|
|
Loads the 4 byte word stored from: MEM[$2+CONST] into a Coprocessor data register. Sign extension. |
| Store word coprocessor |
swcZ $x,CONST ($y) |
Memory[$y + CONST] = Coprocessor[Z].DataRegister[$x] |
I |
|
|
Stores the 4 byte word held by a Coprocessor data register into: MEM[$2+CONST]. Sign extension. |
| Logical |
FP compare single (eq,ne,lt,le,gt,ge) |
c.lt.s $f2,$f4 |
if ($f2 < $f4) cond=1; else cond=0 |
|
|
|
Floating-point compare less than single precision |
| FP compare double (eq,ne,lt,le,gt,ge) |
c.lt.d $f2,$f4 |
if ($f2 < $f4) cond=1; else cond=0 |
|
|
|
Floating-point compare less than double precision |
| Branch |
branch on FP true |
bc1t 100 |
if (cond 1) go to PC+4+100 |
|
|
|
PC relative branch if FP condition |
| branch on FP false |
bc1f 100 |
if (cond 0) go to PC+4+100 |
|
|
|
PC relative branch if not condition |
Pseudo instructions
These instructions are accepted by the MIPS assembler, although they are not real instructions within the MIPS instruction set. Instead, the assembler translates them into sequences of real instructions.
| Name | instruction syntax | Real instruction translation | meaning |
| Move |
move $rt,$rs |
addi $rt,$rs,0 |
R[rt]=R[rs] |
| Clear |
clear $rt |
add $rt,$zero,$zero |
R[rt]=0 |
| Load Address |
la $rd, LabelAddr |
lui $rd, LabelAddr[31:16]; ori $rd,$rd, LabelAddr[15:0] |
$rd = Label Address |
| Load Immediate |
li $rd, IMMED[31:0] |
lui $rd, IMMED[31:16]; ori $rd,$rd, IMMED[15:0] |
$rd = 32 bit Immediate value |
| Branch unconditionally |
b Label |
beq $zero,$zero,Label |
if(R[rs]R[rt]) PC=Label |
| Branch and link |
bal $rs,Label |
bgezal $zero,Label |
if(R[rs]>=0) PC=Label |
| Branch if greater than |
bgt $rs,$rt,Label |
slt $at,$rt,$rs; bne $at,$zero,Label |
if(R[rs]>R[rt]) PC=Label |
| Branch if less than |
blt $rs,$rt,Label |
slt $at,$rs,$rt; bne $at,$zero,Label |
if(R[rs]
|
| Branch if greater than or equal |
bge $rs,$rt,Label |
slt $at,$rs,$rt; beq $at,$zero,Label |
if(R[rs]>=R[rt]) PC=Label |
| Branch if less than or equal |
ble $rs,$rt,Label |
slt $at,$rt,$rs; beq $at,$zero,Label |
if(R[rs]<=R[rt]) PC=Label |
| Branch if greater than unsigned |
bgtu $rs,$rt,Label |
|
if(R[rs]>R[rt]) PC=Label |
| Branch if greater than zero |
bgtz $rs,$rt,Label |
|
if(R[rs]>0) PC=Label |
| Multiplies and returns only first 32 bits |
mul $d, $s, $t |
mult $s, $t; mflo $d |
$d = $s * $t |
| Divides and returns quotient |
div $d, $s, $t |
div $s, $t; mflo $d |
$d = $s / $t |
| Divides and returns remainder |
rem $d, $s, $t |
div $s, $t; mfhi $d |
$d = $s % $t |
Other instructions
- NOP
In computer science, NOP or NOOP is an assembly language instruction, sequence of programming language statements, or computer protocol command that effectively does nothing at all....
(no operation) (machine code 0x00000000, interpreted by CPU as sll $0,$0,0)
- break (breaks the program, used by debuggers)
- syscall (used for system calls to the operating system)
Compiler register usage
The hardware architecture specifies that:
- General purpose register $0 always returns a value of 0.
- General purpose register $31 is used as the link register for jump and link instructions.
- HI and LO are used to access the multiplier/divider results, accessed by the mfhi (move from high) and mflo commands.
These are the only hardware restrictions on the usage of the general purpose registers.
The various MIPS tool-chains implement specific calling conventions that further restrict how
the registers are used. These
calling conventionIn computer science, a calling convention is a scheme for how subroutines receive parameters from their caller and how they return a result; calling conventions can differ in:...
s are totally maintained by the tool-chain software
and are not required by the hardware.
Registers for O32 Calling Convention
| Name |
Number |
Use |
Callee must preserve? |
| $zero |
$0 |
constant 0 |
N/A |
| $at |
$1 |
assembler temporary |
|
| $v0–$v1 |
$2–$3 |
values for function returns and expression evaluation |
|
| $a0–$a3 |
$4–$7 |
function arguments |
|
| $t0–$t7 |
$8–$15 |
temporaries |
|
| $s0–$s7 |
$16–$23 |
saved temporaries |
|
| $t8–$t9 |
$24–$25 |
temporaries |
|
| $k0–$k1 |
$26–$27 |
reserved for OS kernel |
N/A |
| $gp |
$28 |
global pointer |
|
| $sp |
$29 |
stack pointer Stacks in computing architectures are regions of memory where data is added or removed in a last-in-first-out manner.In most modern computer systems, each thread has a reserved region of memory referred to as its stack. When a function executes, it may add some of its state data to the top of the...
|
|
| $fp |
$30 |
frame pointer |
|
| $ra |
$31 |
return address In computer programming, a return statement causes execution to leave the current subroutine and resume at the point in the code immediately after where the subroutine was called, known as its return address. The return address is saved, usually on the process's call stack, as part of the operation...
|
N/A |
Registers for N32 and N64 Calling Conventions
| Name |
Number |
Use |
Callee must preserve? |
| $zero |
$0 |
constant 0 |
N/A |
| $at |
$1 |
assembler temporary |
|
| $v0–$v1 |
$2–$3 |
values for function returns and expression evaluation |
|
| $a0–$a7 |
$4–$11 |
function arguments |
|
| $t4–$t7 |
$12–$15 |
temporaries |
|
| $s0–$s7 |
$16–$23 |
saved temporaries |
|
| $t8–$t9 |
$24–$25 |
temporaries |
|
| $k0–$k1 |
$26–$27 |
reserved for OS kernel |
N/A |
| $gp |
$28 |
global pointer |
|
| $sp |
$29 |
stack pointer Stacks in computing architectures are regions of memory where data is added or removed in a last-in-first-out manner.In most modern computer systems, each thread has a reserved region of memory referred to as its stack. When a function executes, it may add some of its state data to the top of the...
|
|
| $s8 |
$30 |
frame pointer |
|
| $ra |
$31 |
return address In computer programming, a return statement causes execution to leave the current subroutine and resume at the point in the code immediately after where the subroutine was called, known as its return address. The return address is saved, usually on the process's call stack, as part of the operation...
|
N/A |
Registers that are preserved across a call are registers that (by convention) will not be changed by a system call or procedure (function) call. For example, $s-registers must be saved to the stack by a procedure that needs to use them, and $sp and $fp are always incremented by constants, and decremented back after the procedure is done with them (and the memory they point to). By contrast, $ra is changed automatically by any normal function call (ones that use jal), and $t-registers must be saved by the program before any procedure call (if the program needs the values inside them after the call).
Simulators
Open Virtual Platforms (OVP) includes the freely available for non-commercial use simulator
OVPsimOVPsim is a multiprocessor platform emulator that uses dynamic binary translation technology to achieve high simulation speeds. It has public APIs allowing users to create their own processor, peripheral and platform models. Various models are available as source . OVPsim is a key component of the...
, a library of models of processors, peripherals and platforms, and APIs which enable users to develop their own models. The models in the library are open source, written in C, and include the MIPS 4K, 24K, 34K, 74K, 1004K, 1074K, and M14K cores. These models are created and maintained by Imperas and in partnership with MIPS Technologies have been tested and assigned the MIPS-Verified (tm) mark. Sample MIPS-based platforms include both bare metal environments and platforms for booting unmodified Linux binary images. These platforms–emulators are available as source or binaries and are fast, free, and easy to use.
OVPsimOVPsim is a multiprocessor platform emulator that uses dynamic binary translation technology to achieve high simulation speeds. It has public APIs allowing users to create their own processor, peripheral and platform models. Various models are available as source . OVPsim is a key component of the...
is developed and maintained by Imperas and is very fast (hundreds of million of instructions per second), and built to handle multicore architectures.
There is a freely available MIPS32 simulator (earlier versions simulated only the R2000/R3000) called
SPIMSPIM is a MIPS processor simulator, designed to run assembly language code for this architecture. The program simulates R2000 and R3000 processors, and was written by James R. Larus while a professor at the University of Wisconsin-Madison...
for use in education. EduMIPS64 is a GPL graphical cross-platform MIPS64 CPU simulator, written in Java/Swing. It supports a wide subset of the MIPS64 ISA and allows the user to graphically see what happens in the pipeline when an assembly program is run by the CPU. It has educational purposes and is used in some computer architecture courses in universities around the world.
MARS is another GUI-based MIPS emulator designed for use in education, specifically for use with Hennessy's
Computer Organization and Design.
WebMIPS is a browser based MIPS simulator with visual representation of a generic, pipelined processor. This simulator is quite useful for register tracking during step by step execution.
More advanced free emulators are available from the
GXemulGXemul is a computer architectureemulator being developed by Anders Gavare. It isavailable as free software under a revised BSD-style license.In 2005, Gavare changed the name of the software project...
(formerly known as the mips64emul project) and
QEMUQEMU is a processor emulator that relies on dynamic binary translation to achieve a reasonable speed while being easy to port on new host CPU architectures....
projects. These emulate the various MIPS III and IV microprocessors in addition to entire computer systems which use them.
Commercial simulators are available especially for the embedded use of MIPS processors, for example Virtutech
SimicsSimics is a full-system simulator used to run unchanged production binaries of the target hardware at high-performance speeds. Simics was originally developed by the Swedish Institute of Computer Science , and then spun off to Virtutech for commercial development in 1998...
(MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000), VaST Systems (R3000, R4000), and
CoWareCoWare, now part of Synopsys, was a supplier of platform-driven electronic system level design software and services.CoWare was headquartered in San Jose, California, and had offices around the world, major R&D offices in Belgium, Germany and India....
(the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K).
See also
- DLX
The DLX is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the MIPS and the Berkeley RISC designs , the two benchmark examples of RISC design. The DLX is essentially a cleaned up and simplified MIPS, with a simple 32-bit load/store...
, a very similar architecture designed by John L. HennessyJohn LeRoy Hennessy is an American computer scientist and academician. Hennessy is one of the founders of MIPS Computer Systems Inc. and is the 10th President of Stanford University.-Background:...
(creator of MIPS) for teaching purposes
- MIPS-X
MIPS-X is a microprocessor and instruction set architecture developed as a follow-on project to the MIPS architecture at Stanford University by the same team that developed MIPS. The project, supported by the Defense Advanced Research Projects Agency, started in 1984, and its final form was...
, developed as a follow-on project to the MIPS architecture
External links