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MOS Technology 8568
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The 8568 Video Display Controller (VDC), less commonly known as the DVDC, D = "Digital", was MOS Technology's graphics chip responsible for the "80 column" (or RGBI) display on D[CR] models of the Commodore 128 personal computer. In the Commodore 128 service manual, this part was referred to as the "80 column CRT controller." The 8568 embodied many of the features of the older 6545E monochrome CRT controller plus RGBI color.
The original ("flat") C128 used the 8563 VDC chip.
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The 8568 Video Display Controller (VDC), less commonly known as the DVDC, D = "Digital", was MOS Technology's graphics chip responsible for the "80 column" (or RGBI) display on D[CR] models of the Commodore 128 personal computer. In the Commodore 128 service manual, this part was referred to as the "80 column CRT controller." The 8568 embodied many of the features of the older 6545E monochrome CRT controller plus RGBI color.
The original ("flat") C128 used the 8563 VDC chip. The 8568 was essentially an updated version of the 8563, combining the latter's functionality with logic that previously was implemented by discrete components in physical proximity to the 8563. Unlike the 8563, the 8568 included an unused active low interrupt request line (/INTR), which was asserted when the "ready" bit in the 8568's status register changed from 0 to 1. Reading the control register would automatically deassert /INTR. Owing to differences in pin assignments and circuit interfacing, the 8563 and 8568 are not electrically interchangeable.
The Commodore 128 had two video display modes, which were usually used singularly, but could be used simultaneously if the computer was connected to two compatible video monitors. The VIC-II chip, also found in the Commodore 64, was mapped directly into main memory—that is, the video memory and CPUs (the 8502 and Z80A processors) shared a common 128 KB RAM, and the VIC-II control registers were accessed as memory locations (that is, they were memory mapped).
Unlike the VIC-II, the 8568 (and the 8563) had its own local video RAM, 64K in the C-128DCR model (sold in North America) and, depending on the date of manufacture of the particular machine, either 16 or 64K in the C-128D model (marketed in Europe). Access to this video RAM or any of the 8568's internal registers was accomplished through two external, memory mapped hardware registers: the control/status register at 0xD600, and the data I/O register at 0xD601. A typical 6502 assembly language program to read an internal VDC register would be as follows:
ldx #regnum ;VDC register to access
stx $d600 ;write to control register
loop bit $d600 ;check bit 7 of status register
bpl loop ;VDC not ready
lda $d601 ;get contents of VDC register
Owing to this indirect method of controlling the VDC, the rate at which the display could be changed when in bit mapped mode was generally too slow for use in arcade style video games, where bit-intensive manipulation of the display is required.
Register Listing
This information was adapted from the
| Register | Hexadecimal | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Description |
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| 0 | $00 | HT7 | HT6 | HT5 | HT4 | HT3 | HT2 | HT1 | HT0 | Horizontal Total | | 1 | $01 | HD7 | HD6 | HD5 | HD4 | HD3 | HD2 | HD1 | HD0 | Horizontal Displayed | | 2 | $02 | HP7 | HP6 | HP5 | HP4 | HP3 | HP2 | HP1 | HP0 | Horizontal Sync Position | | 3 | $03 | VW3 | VW2 | VW1 | VW0 | HW3 | HW2 | HW1 | HW0 | Vertical/Horizontal Sync Width | | 4 | $04 | VT7 | VT6 | VT5 | VT4 | VT3 | VT2 | VT1 | VT0 | Vertical Total | | 5 | $05 | -- | -- | -- | VA4 | VA3 | VA2 | VA1 | VA0 | Vertical Adjust | | 6 | $06 | VD7 | VD6 | VD5 | VD4 | VD3 | VD2 | VD1 | VD0 | Vertical Displayed | | 7 | $07 | VP7 | VP6 | VP5 | VP4 | VP3 | VP2 | VP1 | VP0 | Vertical Sync Position | | 8 | $08 | -- | -- | -- | -- | -- | -- | IM1 | IM0 | Interlace Mode | | 9 | $09 | -- | -- | -- | -- | CTV4 | CTV3 | CTV2 | CTV1 | Character Total Vertical | | 10 | $0A | -- | CM1 | CM0 | CS4 | CS3 | CS2 | CS1 | CS0 | Cursor Mode, Start Scan | | 11 | $0B | -- | -- | -- | CE4 | CE3 | CE2 | CE1 | CE0 | Cursor End Scan Line | | 12 | $0C | DS15 | DS14 | DS13 | DS12 | DS11 | DS10 | DS9 | DS8 | Display Start Address High Byte | | 13 | $0D | DS7 | DS6 | DS5 | DS4 | DS3 | DS2 | DS1 | DS0 | Display Start Address Low Byte | | 14 | $0E | CP15 | CP14 | CP13 | CP12 | CP11 | CP10 | CP9 | CP8 | Cursor Position High Byte | | 15 | $0F | CP7 | CP6 | CP5 | CP4 | CP3 | CP2 | CP1 | CP0 | Cursor Position Low Byte | | 16 | $10 | LPV7 | LPV6 | LPV5 | LPV4 | LPV3 | LPV2 | LPV1 | LPV0 | Light Pen Vertical Position | | 17 | $11 | LPH7 | LPH6 | LPH5 | LPH4 | LPH3 | LPH2 | LPH1 | LPH0 | Light Pen Horizontal Position | | 18 | $12 | UA15 | UA14 | UA13 | UA12 | UA11 | UA10 | UA9 | UA8 | Update Address High Byte | | 19 | $13 | UA7 | UA6 | UA5 | UA4 | UA3 | UA2 | UA1 | UA0 | Update Address Low Byte | | 20 | $14 | AA15 | AA14 | AA13 | AA12 | AA11 | AA10 | AA9 | AA8 | Attribute Start Address High Byte | | 21 | $15 | AA7 | AA6 | AA5 | AA4 | AA3 | AA2 | AA1 | AA0 | Attribute Start Address Low Byte | | 22 | $16 | CTH3 | CTH2 | CTH1 | CTH0 | CDH3 | CDH2 | CDH1 | CDH0 | Character Total Horizontal, Character Display Horizontal | | 23 | $17 | -- | -- | -- | CDV4 | CDV3 | CDV2 | CDV1 | CDV0 | Character Display Vertical | | 24 | $18 | COPY | RVS | CBRATE | VSS4 | VSS3 | VSS2 | VSS1 | VSS0 | Vertical Smooth Scrolling | | 25 | $19 | TEXT | ATR | SEMI | DBL | HSS3 | HSS2 | HSS1 | HSS0 | Horizontal Smooth Scrolling | | 26 | $1A | FG3 | FG2 | FG1 | FG0 | BG3 | BG2 | BG1 | BG0 | Foreground/Background color | | 27 | $1B | AI7 | AI6 | AI5 | AI4 | AI3 | AI2 | AI1 | AI0 | Address Increment per Row | | 28 | $1C | CB15 | CB14 | CB13 | RAM | -- | -- | -- | -- | Character Base Address | | 29 | $1D | -- | -- | -- | UL4 | UL3 | UL2 | UL1 | UL0 | Underline Scan Line | | 30 | $1E | WC7 | WC6 | WC5 | WC4 | WC3 | WC2 | WC1 | WC0 | Word Count | | 31 | $1F | DA7 | DA6 | DA5 | DA4 | DA3 | DA2 | DA1 | DA0 | Data Register | | 32 | $20 | BA15 | BA14 | BA13 | BA12 | BA11 | BA10 | BA9 | BA8 | Block Start Address High Byte | | 33 | $21 | BA7 | BA6 | BA5 | BA4 | BA3 | BA2 | BA1 | BA0 | Block Start Address Low Byte | | 34 | $22 | DEB7 | DEB6 | DEB5 | DEB4 | DEB3 | DEB2 | DEB1 | DEB0 | Display Enable Begin | | 35 | $23 | DEE7 | DEE6 | DEE5 | DEE4 | DEE3 | DEE2 | DEE1 | DEE0 | Display Enable End | | 36 | $24 | -- | -- | -- | -- | DRR3 | DRR2 | DRR1 | DRR0 | DRAM Refresh Rate | | 37 | $25 | HSYNC | VSYNC | -- | -- | -- | -- | -- | -- | SYNC Polarity |
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