Uncore
Encyclopedia
The uncore is a term used by Intel to describe the functions of a microprocessor
that are not in the Core, but which are essential for Core performance. The Core contains the components of the processor involved in executing instructions, including the ALU
, FPU
, L1 and L2 cache. Uncore functions include QPI controllers, L3 cache, snoop agent
pipeline
, on-die memory controller
, and Thunderbolt controller. Other bus controllers such as PCI Express
and SPI
are part of the chipset
.
The Intel Uncore design stems from its origin as the Northbridge
. The design of the Intel Uncore reorganizes the functions critical to the Core, making them physically closer to the Core on-die, thereby reducing their access latency. Functions from the Northbridge which are less essential for the Core, such as PCI Express or the Power Control Unit (PCU), are not integrated into the Uncore -- they remain as part of the Chipset.
Specifically, the micro-architecture
of the Intel Uncore is broken down into a number of modular units. The main Uncore interface to the Core is the Cache Box (CBox), which interfaces with the LLC and is responsible for managing cache coherency
. Multiple internal and external QPI links are managed by Physical Layer units, referred to as PBox. Connections between the PBox, CBox, and one or more iMC's (MBox) are managed by System Config Controller (UBox) and a Router (RBox).
Removal of serial bus controllers from the Intel Uncore further enables increased performance by allowing the Uncore clock (UCLK) to run at a base of 2.66 GHz, with upwards overclocking limits in excess of 3.44 GHz. This increased clock rate allows the Core to access critical functions (such as the iMC
) with significantly less latency (typically reducing Core access to DRAM by 10ns or more).
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
that are not in the Core, but which are essential for Core performance. The Core contains the components of the processor involved in executing instructions, including the ALU
Arithmetic logic unit
In computing, an arithmetic logic unit is a digital circuit that performs arithmetic and logical operations.The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers...
, FPU
Floating point unit
A floating-point unit is a part of a computer system specially designed to carry out operations on floating point numbers. Typical operations are addition, subtraction, multiplication, division, and square root...
, L1 and L2 cache. Uncore functions include QPI controllers, L3 cache, snoop agent
Memory coherence
Memory coherence is an issue that affects the design of computer systems in which two or more processors or cores share a common area of memory....
pipeline
Instruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
, on-die memory controller
Memory controller
The memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
, and Thunderbolt controller. Other bus controllers such as PCI Express
PCI Express
PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...
and SPI
Serial Peripheral Interface Bus
The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select ...
are part of the chipset
Chipset
A chipset, PC chipset, or chip set refers to a group of integrated circuits, or chips, that are designed to work together. They are usually marketed as a single product.- Computers :...
.
The Intel Uncore design stems from its origin as the Northbridge
Northbridge (computing)
The northbridge has historically been one of the two chips in the core logic chipset on a PC motherboard, the other being the southbridge. Increasingly these functions have migrated to the CPU chip itself, beginning with memory and graphics controllers. For Intel Sandy Bridge and AMD Fusion...
. The design of the Intel Uncore reorganizes the functions critical to the Core, making them physically closer to the Core on-die, thereby reducing their access latency. Functions from the Northbridge which are less essential for the Core, such as PCI Express or the Power Control Unit (PCU), are not integrated into the Uncore -- they remain as part of the Chipset.
Specifically, the micro-architecture
Microarchitecture
In computer engineering, microarchitecture , also called computer organization, is the way a given instruction set architecture is implemented on a processor. A given ISA may be implemented with different microarchitectures. Implementations might vary due to different goals of a given design or...
of the Intel Uncore is broken down into a number of modular units. The main Uncore interface to the Core is the Cache Box (CBox), which interfaces with the LLC and is responsible for managing cache coherency
Cache coherence
In computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...
. Multiple internal and external QPI links are managed by Physical Layer units, referred to as PBox. Connections between the PBox, CBox, and one or more iMC's (MBox) are managed by System Config Controller (UBox) and a Router (RBox).
Removal of serial bus controllers from the Intel Uncore further enables increased performance by allowing the Uncore clock (UCLK) to run at a base of 2.66 GHz, with upwards overclocking limits in excess of 3.44 GHz. This increased clock rate allows the Core to access critical functions (such as the iMC
Memory controller
The memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
) with significantly less latency (typically reducing Core access to DRAM by 10ns or more).