Serial Peripheral Interface Bus
Encyclopedia


The Serial Peripheral Interface Bus or SPI bus is a synchronous
Synchronization (computer science)
In computer science, synchronization refers to one of two distinct but related concepts: synchronization of processes, and synchronization of data. Process synchronization refers to the idea that multiple processes are to join up or handshake at a certain point, so as to reach an agreement or...

 serial data link
Serial communications
In telecommunication and computer science, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are sent as a whole, on a link with several parallel channels...

 standard named by Motorola
Motorola
Motorola, Inc. was an American multinational telecommunications company based in Schaumburg, Illinois, which was eventually divided into two independent public companies, Motorola Mobility and Motorola Solutions on January 4, 2011, after losing $4.3 billion from 2007 to 2009...

 that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame
Data frame
In computer networking and telecommunication, a frame is a digital data transmission unit or data packet that includes frame synchronization, i.e. a sequence of bits or symbols making it possible for the receiver to detect the beginning and end of the packet in the stream of symbols or bits...

. Multiple slave devices are allowed with individual slave select (chip select
Chip select
Chip select or slave select is the name of a control line in digital electronics used to select one chip out of several connected to the same computer bus usually utilizing the three-state logic....

) lines. Sometimes SPI is called a "four-wire" serial bus, contrasting with three-, two-, and one-wire
1-Wire
1-Wire is a device communications bus system designed by Dallas Semiconductor Corp. that provides low-speed data, signaling, and power over a single signal. 1-Wire is similar in concept to I²C, but with lower data rates and longer range. It is typically used to communicate with small inexpensive...

 serial buses.

Interface

The SPI bus specifies four logic signals:
  • SCLK: Serial Clock (output from master);
  • MOSI; SIMO: Master Output, Slave Input (output from master);
  • MISO; SOMI: Master Input, Slave Output (output from slave);
  • SS: Slave Select (active low
    Logic level
    In digital circuits, a logic level is one of a finite number of states that a signal can have. Logic levels are usually represented by the voltage difference between the signal and ground , although other standards exist...

    , output from master).


Alternative naming conventions are also widely used:
  • SCK; CLK: Serial Clock (output from master)
  • SDI; DI, DIN, SI: Serial Data In; Data In, Serial In
  • SDO; DO, DOUT, SO: Serial Data Out; Data Out, Serial Out
  • nCS, CS, CSB, CSN, nSS, STE: Chip Select
    Chip select
    Chip select or slave select is the name of a control line in digital electronics used to select one chip out of several connected to the same computer bus usually utilizing the three-state logic....

    , Slave Transmit Enable (active low
    Logic level
    In digital circuits, a logic level is one of a finite number of states that a signal can have. Logic levels are usually represented by the voltage difference between the signal and ground , although other standards exist...

    , output from master)


The SDI/SDO (DI/DO, SI/SO) convention requires that SDO on the master be connected to SDI on the slave, and vice-versa. Chip select polarity is rarely active high, although some notations (such as SS or CS instead of nSS or nCS) suggest otherwise.
SPI port pin names for particular IC products may differ from those depicted in these illustrations.

Operation

The SPI bus can operate with a single master device and with one or more slave devices.

If a single slave device is used, the SS pin may be fixed to logic low
Logic level
In digital circuits, a logic level is one of a finite number of states that a signal can have. Logic levels are usually represented by the voltage difference between the signal and ground , although other standards exist...

 if the slave permits it. Some slaves require the falling edge (high→low transition) of the chip select to initiate an action such as the Maxim
Maxim Integrated Products
Maxim Integrated Products is a publicly traded company that designs, manufactures, and sells analog and mixed-signal semiconductor products. Maxim develops integrated circuits for the industrial, communications, consumer, and computing markets....

 MAX1242 ADC
Analog-to-digital converter
An analog-to-digital converter is a device that converts a continuous quantity to a discrete time digital representation. An ADC may also provide an isolated measurement...

, which starts conversion on said transition. With multiple slave devices, an independent SS signal is required from the master for each slave device.

Most slave devices have tri-state outputs so their MISO signal becomes high impedance
High impedance
In electronics, high impedance means that a point in a circuit has a relatively high impedance to other points in the circuit.-Digital electronics:...

 ("disconnected") when the device is not selected. Devices without tri-state outputs can't share SPI bus segments with other devices; only one such slave could talk to the master, and only its chip select could be activated.

Data transmission

To begin a communication, the master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1–70 MHz.

The master then pulls the chip select low for the desired chip.
If a waiting period is required (such as for analog-to-digital conversion) then the master must wait for at least that period of time before starting to issue clock cycles.

During each SPI clock cycle, a full duplex data transmission occurs:
  • the master sends a bit on the MOSI line; the slave reads it from that same line
  • the slave sends a bit on the MISO line; the master reads it from that same line


Not all transmissions require all four of these operations to be meaningful but they do happen.

Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a ring.
Data are usually shifted out with the most significant bit first, while shifting a new least significant bit into the same register.
After that register has been shifted out, the master and slave have exchanged register values.
Then each device takes that value and does something with it, such as writing it to memory.
If there are more data to exchange, the shift registers are loaded with new data and the process repeats.

Transmissions may involve any number of clock cycles. When there are no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave.

Transmissions often consist of 8-bit words, and a master can initiate multiple such transmissions if it wishes/needs. However, other word sizes are also common, such as 16-bit words for touchscreen controllers or audio codecs, like the TSC2101 from Texas Instruments
Texas Instruments
Texas Instruments Inc. , widely known as TI, is an American company based in Dallas, Texas, United States, which develops and commercializes semiconductor and computer technology...

; or 12-bit words for many digital-to-analog or analog-to-digital converters.

Every slave on the bus that hasn't been activated using its chip select line must disregard the input clock and MOSI signals, and must not drive MISO. The master must select only one slave at a time.

Clock polarity and phase

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescale's SPI Block Guide names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention.

The timing diagram
Digital Timing Diagram
A Digital timing diagram is a representation of a set of signals in the time domain. A timing diagram can contain many rows, usually one of them being the clock. It is a tool that is ubiquitous in digital electronics, hardware debugging, and digital communications...

 is shown to the right. The timing is further described below and applies to both the master and the slave device.
  • At CPOL=0 the base value of the clock is zero
    • For CPHA=0, data are captured on the clock's rising edge (low→high transition) and data are propagated on a falling edge (high→low clock transition).
    • For CPHA=1, data are captured on the clock's falling edge and data are propagated on a rising edge.
  • At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
    • For CPHA=0, data are captured on clock's falling edge and data are propagated on a rising edge.
    • For CPHA=1, data are captured on clock's rising edge and data are propagated on a falling edge.


That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle. For all CPOL and CPHA modes, the initial clock value must be stable before the chip select line goes active.

Also, note that "data are read" in this document more typically means "data may be read". The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle.

This adds more flexibility to the communication channel between the master and slave.

Some products use different naming conventions. For example, the TI MSP430
TI MSP430
The MSP430 is a mixed-signal microcontroller family from Texas Instruments. Built around a 16-bit CPU, the MSP430 is designed for low cost, and specifically, low power consumption embedded applications. The architecture dates from the 1990s and is reminiscent of the DEC PDP-11.-Applications:The...

 uses the name UCCKPL instead of CPOL, and its UCCKPH is the inverse of CPHA. When connecting two chips together, carefully examine the clock phase initialization values to be sure of using the right settings.

Mode numbers

The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention, with CPOL as the high order bit and CPHA as the low order bit:
ModeCPOLCPHA
0 0 0
1 0 1
2 1 0
3 1 1


Another commonly used notation represents the mode as a (CPOL,CPHA) tuple, e.g. the value '(0,1)' would indicate CPOL=0 and CPHA=1

Independent slave SPI configuration

In the independent slave configuration, there is an independent chip select line for each slave. This is the way SPI is normally used. Since the MISO pins of the slaves are connected together, they are required to be tri-state pins.

Daisy chain SPI configuration

Some products with SPI bus are designed to be capable of being connected in a daisy chain
Daisy chain (electrical engineering)
In electrical and electronic engineering a daisy chain is a wiring scheme in which multiple devices are wired together in sequence or in a ring...

 configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of what it received during the first group of clock pulses. The whole chain acts as an SPI communication shift register
Shift register
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, which has the output of any one but the last flip-flop connected to the "data" input of the next one in the chain, resulting in a circuit that shifts by one position the one-dimensional "bit array" stored in...

; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Such a feature only requires a single SS line from the master, rather than a separate SS line for each slave.

Applications (discussed later) that require a daisy chain configuration include SGPIO
SGPIO
SGPIO is an acronym for Serial General Purpose Input/Output which is a 4-signal bus used between a host bus adapter and a backplane; of the 4 signals, 3 are driven by the HBA and 1 by the backplane...

 and JTAG
JTAG
Joint Test Action Group is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.Today JTAG is also...

.

Valid SPI communications

Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others don't care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access the scan chain
Scan chain
Scan chain is a technique used in Design For Test. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC.The basic structure of scan include the following set of signals in order to control and observe the scan mechanism.#Scan_in and scan_out...

 of a digital IC by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain).

Interrupts

SPI devices sometimes use another signal line to send an interrupt signal to a host CPU. Examples include pen-down interrupts from touchscreen sensors, thermal limit alerts from temperature sensors, alarms issued by real time clock chips, SDIO, and headset jack insertions from the sound codec in a cell phone. Interrupts are not covered by the SPI standard; their usage is neither forbidden nor specified by the standard.

Example of bit-banging the SPI master protocol

Below is an example of bit-banging
Bit-banging
Bit banging is a technique for serial communications using software instead of dedicated hardware. Software directly sets and samples the state of pins on the microcontroller, and is responsible for all parameters of the signal: timing, levels, synchronization, etc...

 the SPI protocol as an SPI master with CPOL=0, CPHA=0, and eight bits per transfer. The example is written in the C programming language. Because this is CPOL=0 the clock must be pulled low before the chip select is activated. The chip select line must be activated, which normally means being toggled low, for the peripheral before the start of the transfer, and then deactivated afterwards. Most peripherals allow or require several transfers while the select line is low; this routine might be called several times before deselecting the chip.


unsigned char SPIBitBang8BitsMode0(unsigned char byte)
{
unsigned char bit;

for (bit = 0; bit < 8; bit++) {
/* write MOSI on trailing edge of previous clock */
if (byte & 0x80)
SETMOSI;
else
CLRMOSI;
byte <<= 1;

/* half a clock cycle before leading/rising edge */
SPIDELAY(SPISPEED/2);
SETCLK;

/* half a clock cycle before trailing/falling edge */
SPIDELAY(SPISPEED/2);

/* read MISO on trailing edge */
byte |= READMISO;
CLRCLK;
}

return byte;
}

Advantages

  • Full duplex communication
  • Higher throughput than I²C
    I²C
    I²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...

     or SMBus
    System Management Bus
    The System Management Bus is a single-ended simple two-wire bus for the purpose of lightweight communication...

  • Complete protocol flexibility for the bits transferred
    • Not limited to 8-bit words
    • Arbitrary choice of message size, content, and purpose
  • Extremely simple hardware interfacing
    • Typically lower power requirements than I²C or SMBus due to less circuitry (including pullups)
    • No arbitration or associated failure modes
    • Slaves use the master's clock, and don't need precision oscillators
    • Slaves don't need a unique address
      Address space
      In computing, an address space defines a range of discrete addresses, each of which may correspond to a network host, peripheral device, disk sector, a memory cell or other logical or physical entity.- Overview :...

       -- unlike I²C
      I²C
      I²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...

       or GPIB or SCSI
      SCSI
      Small Computer System Interface is a set of standards for physically connecting and transferring data between computers and peripheral devices. The SCSI standards define commands, protocols, and electrical and optical interfaces. SCSI is most commonly used for hard disks and tape drives, but it...

    • Transceivers are not needed
  • Uses only four pins on IC packages, and wires in board layouts or connectors, much less than parallel interfaces
  • At most one "unique" bus signal per device (chip select); all others are shared
  • Signals are unidirectional allowing for easy Galvanic isolation
    Galvanic isolation
    Galvanic isolation is a principle of isolating functional sections of electrical systems, thus preventing the movement of charge-carrying particles from one section to another, i.e. no direct current flows between the sections. Energy or information can still be exchanged between the sections by...


Disadvantages

  • Requires more pins on IC packages than I²C
    I²C
    I²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...

    , even in the "3-Wire" variant
  • No in-band addressing; out-of-band chip select
    Chip select
    Chip select or slave select is the name of a control line in digital electronics used to select one chip out of several connected to the same computer bus usually utilizing the three-state logic....

     signals are required on shared buses
  • No hardware flow control
    Flow control
    In data communications, flow control is the process of managing the pacing of data transmission between two nodes to prevent a fast sender from outrunning a slow receiver. It provides a mechanism for the receiver to control the transmission speed, so that the receiving node is not overwhelmed with...

     by the slave (but the master can delay the next clock edge to slow the transfer rate)
  • No hardware slave acknowledgment (the master could be "talking" to nothing and not know it)
  • Supports only one master device
  • No error-checking protocol is defined
  • Generally prone to noise spikes causing faulty communication
  • Without a formal standard, validating conformance is not possible
  • Only handles short distances compared to RS-232
    RS-232
    In telecommunications, RS-232 is the traditional name for a series of standards for serial binary single-ended data and control signals connecting between a DTE and a DCE . It is commonly used in computer serial ports...

    , RS-485, or CAN-bus
  • Many existing variations, making it difficult to find development tools like host adapters that support those variations

Applications

The board real estate savings compared to a parallel I/O bus are significant, and have earned SPI a solid role in embedded systems. That is true for most system-on-a-chip
System-on-a-chip
A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...

 processors, both with higher end 32-bit processors such as those using ARM
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...

, MIPS
MIPS architecture
MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...

, or PowerPC
PowerPC
PowerPC is a RISC architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM...

 and with other microcontrollers such as the AVR
Atmel AVR
The AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other...

, PIC
PIC microcontroller
PIC is a family of Harvard architecture microcontrollers made by Microchip Technology, derived from the PIC1650 originally developed by General Instrument's Microelectronics Division...

, and MSP430. These chips usually include SPI controllers capable of running in either master or slave mode. In-system programmable AVR controllers (including blank ones) can be programmed using an SPI interface.

Chip or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin.

The full-duplex capability makes SPI very simple and efficient for single master/single slave applications. Some devices use the full-duplex mode to implement an efficient, swift data stream for applications such as digital audio
Digital audio
Digital audio is sound reproduction using pulse-code modulation and digital signals. Digital audio systems include analog-to-digital conversion , digital-to-analog conversion , digital storage, processing and transmission components...

, digital signal processing
Digital signal processing
Digital signal processing is concerned with the representation of discrete time signals by a sequence of numbers or symbols and the processing of these signals. Digital signal processing and analog signal processing are subfields of signal processing...

, or telecommunications channels
Channel (communications)
In telecommunications and computer networking, a communication channel, or channel, refers either to a physical transmission medium such as a wire, or to a logical connection over a multiplexed medium such as a radio channel...

, but most off-the-shelf chips stick to half-duplex request/response protocols.

SPI is used to talk to a variety of peripherals, such as
  • Sensors: temperature, pressure, ADC
    Analog-to-digital converter
    An analog-to-digital converter is a device that converts a continuous quantity to a discrete time digital representation. An ADC may also provide an isolated measurement...

    , touchscreens, video game controllers
  • Control devices: audio codec
    Audio codec
    All codecs are devices or computer programs capable of coding or decoding a digital data stream or signal.The term audio codec has two meanings depending on the context:...

    s, digital potentiometers, DAC
    Digital-to-analog converter
    In electronics, a digital-to-analog converter is a device that converts a digital code to an analog signal . An analog-to-digital converter performs the reverse operation...

  • Camera lenses: Canon EF lens mount
    Canon EF lens mount
    Introduced in 1987, the EF lens mount is the standard lens mount on the Canon EOS family of SLR film and digital cameras. EF stands for "Electro-Focus": automatic focusing on EF lenses is handled by a dedicated electric motor built into the lens...

  • Communications: Ethernet, USB, USART, CAN, IEEE 802.15.4
    IEEE 802.15.4
    IEEE 802.15.4 is a standard which specifies the physical layer and media access control for low-rate wireless personal area networks . It is maintained by the IEEE 802.15 working group....

    , IEEE 802.11
    IEEE 802.11
    IEEE 802.11 is a set of standards for implementing wireless local area network computer communication in the 2.4, 3.6 and 5 GHz frequency bands. They are created and maintained by the IEEE LAN/MAN Standards Committee . The base version of the standard IEEE 802.11-2007 has had subsequent...

    , handheld video games
  • Memory: flash and EEPROM
  • Real-time clocks
  • LCD displays, sometimes even for managing image data
  • Any MMC
    MultiMediaCard
    The MultiMediaCard is a flash memory memory card standard. Unveiled in 1997 by Siemens AG and SanDisk, it is based on Toshiba's NAND-based flash memory, and is therefore much smaller than earlier systems based on Intel NOR-based memory such as CompactFlash. MMC is about the size of a postage...

     or SD
    Secure Digital
    Secure Digital is a non-volatile memory card format developed by the SD Card Association for use in portable devices. The SD technology is used by more than 400 brands across dozens of product categories and more than 8,000 models, and is considered the de-facto industry standard.Secure Digital...

     card (including SDIO variant)


For high performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based.

JTAG
JTAG
Joint Test Action Group is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.Today JTAG is also...

 is essentially an application stack for a 3-wire SPI flavor, using different signal names: TCK not SCK, TDI not MOSI, TDO not MISO. It defines a state machine (driven by a TMS signal instead of a chip select line), protocol messages, a core command set, the ability to daisy-chain devices in a "scan chain", and how vendors define new commands. The devices in a scan chain are initially treated as a single device, and transitions on TMS update their state machines; once the individual devices are identified, commands may be issued that affect only one device in that scan chain. Different vendors use different JTAG connectors. Bit strings used in JTAG are often long and not multiples of 8 bit words; for example, a boundary scan reports signal state on each of several hundred pins.

SGPIO
SGPIO
SGPIO is an acronym for Serial General Purpose Input/Output which is a 4-signal bus used between a host bus adapter and a backplane; of the 4 signals, 3 are driven by the HBA and 1 by the backplane...

 is essentially another (incompatible) application stack for SPI designed for particular backplane management activities. SGPIO uses 3-bit messages.

Standards

The SPI bus is a de facto standard
De facto standard
A de facto standard is a custom, convention, product, or system that has achieved a dominant position by public acceptance or market forces...

. However, the lack of a formal standard is reflected in a wide variety of protocol options. Different word sizes are common. Every device defines its own protocol, including whether or not it supports commands at all. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some protocols send the least significant bit first.

Some devices even have minor variances from the CPOL/CPHA modes described above. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device. Many of these "capture clocks" run from the chip select line.

Some devices require an additional flow control signal from slave to master, indicating when data are ready. This leads to a "five wire" protocol instead of the usual four. Such a "ready" or "enable" signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have "dummy bytes" inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters don't support that signal directly, and instead rely on fixed delays.)

Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the JTAG
JTAG
Joint Test Action Group is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.Today JTAG is also...

 or SGPIO
SGPIO
SGPIO is an acronym for Serial General Purpose Input/Output which is a 4-signal bus used between a host bus adapter and a backplane; of the 4 signals, 3 are driven by the HBA and 1 by the backplane...

 protocols, or any other protocol that requires messages that are not multiples of 8 bits.

There are even hardware-level differences. Some chips combine MOSI and MISO into a single data line (SI/SO); this is sometimes called "3-Wire" signaling (in contrast to normal "4-wire" SPI). Another SPI flavor removes the chip select line, managing protocol state machine entry/exit using other methods; this isn't usually called 3-Wire though. Anyone needing an external connector for SPI defines their own -- UEXT
UEXT
Univeral EXTension is a connector layout which includes power and three serials buses: Asynchronous, I2C, SPI. The connector layout was specified by Olimex Ltd and declared an open-project that is royalty-free.-Physical characteristics:...

, JTAG connector, Secure Digital
Secure Digital
Secure Digital is a non-volatile memory card format developed by the SD Card Association for use in portable devices. The SD technology is used by more than 400 brands across dozens of product categories and more than 8,000 models, and is considered the de-facto industry standard.Secure Digital...

 card socket, etc. . Signal levels depend entirely on the chips involved.

Development tools

When developing or troubleshooting systems using SPI, visibility at the level of hardware signals can be important.

Host adapters

There are a number of USB hardware
Hardware
Hardware is a general term for equipment such as keys, locks, hinges, latches, handles, wire, chains, plumbing supplies, tools, utensils, cutlery and machine parts. Household hardware is typically sold in hardware stores....

 solutions to provide computers, running Linux
Linux
Linux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...

, Mac
Macintosh
The Macintosh , or Mac, is a series of several lines of personal computers designed, developed, and marketed by Apple Inc. The first Macintosh was introduced by Apple's then-chairman Steve Jobs on January 24, 1984; it was the first commercially successful personal computer to feature a mouse and a...

, or Windows
Microsoft Windows
Microsoft Windows is a series of operating systems produced by Microsoft.Microsoft introduced an operating environment named Windows on November 20, 1985 as an add-on to MS-DOS in response to the growing interest in graphical user interfaces . Microsoft Windows came to dominate the world's personal...

, SPI master and/or slave capabilities. Many of them also provide scripting and/or programming capabilities (Visual Basic, C/C++, ...).

A SPI Host Adapter lets the user play the role of a master on a SPI bus directly from PC. They are used for embedded system, chip (FPGA/ASIC/SoC) and peripheral testing, programming and debug.

The key parameters of SPI Adapters are: the maximum supported frequency for the serial interface, command-to-command latency and the maximum length for SPI commands. It is possible to find SPI Adapters on the market today that support up to 100 MHz serial interfaces, with virtually unlimited access length.

SPI protocol being a de facto standard, some 'SPI Host Adapters' also have the ability of supporting other protocols beyond the 'traditional 4-wires' SPI (e.g: support of quad-SPI protocol or other custom serial protocol that derive from SPI).

Protocol analyzers

SPI Protocol Analyzers are tools which sample a SPI bus and decode the electrical signals to provide a higher-level view of the data being transmitted on a specific bus.

Oscilloscopes

Every major scope vendor offers scope-based triggering and protocol decode for SPI. Most support 2-, 3-, and 4-wire SPI. The trigger and decode capability is typically offered as a for-pay scope application. SPI signals can be accessed via analog scope channels or with digital MSO channels.

Logic analyzers

When developing and/or troubleshooting the SPI bus, examination of hardware signals can be very important. Logic analyzers are tools which collect, analyze, decode, store signals so people can view the high-speed waveforms at their leisure. Logic analyzers display time-stamps of each signal level change, which can help find protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data and show ASCII data.

Queued serial peripheral interface (QSPI)

The queued serial peripheral interface (QSPI) is one type of SPI controller, not another bus type. It uses a data queue with programmable queue pointers allowing some data transfers without CPU intervention. It also has a wrap-around mode allowing continuous transfers to and from the queue with no CPU intervention. As a result, the peripherals appear to the CPU as memory-mapped
Virtual memory
In computing, virtual memory is a memory management technique developed for multitasking kernels. This technique virtualizes a computer architecture's various forms of computer data storage , allowing a program to be designed as though there is only one kind of memory, "virtual" memory, which...

 parallel devices. This feature is useful in applications such as control of an A/D converter
Analog-to-digital converter
An analog-to-digital converter is a device that converts a continuous quantity to a discrete time digital representation. An ADC may also provide an isolated measurement...

. Other programmable features in QSPI are chip selects and transfer length/delay.

SPI controllers from different vendors support different feature sets; such DMA queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself. Most SPI master controllers integrate support for up to four chip selects, although some require chip selects to be managed separately through GPIO lines.

Microwire

Microwire is essentially a predecessor of SPI. It's a strict subset: half duplex, and using SPI mode 0. (Microwire-Plus supports other SPI modes.) Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs. 20 MHz. Some Microwire chips also support a 3-Wire mode (see below), which fits neatly with the restriction to half duplex.

3-wire serial buses

As mentioned above, one variant of SPI uses single bidirectional data line (Slave Out/Slave IN, called SISO) instead of two unidirectional ones (MOSI and MISO). Clearly, this variant is restricted to a half duplex mode. It tends to be used for lower performance parts, such as small EEPROMs used only during system startup and certain sensors, and Microwire. As of this writing, few SPI master controllers support this mode; although it can often be easily bit-banged
Bit-banging
Bit banging is a technique for serial communications using software instead of dedicated hardware. Software directly sets and samples the state of pins on the microcontroller, and is responsible for all parameters of the signal: timing, levels, synchronization, etc...

 in software.

When someone says a part supports SPI or Microwire, you can normally assume that means the four-wire version.

However, when someone talks about a part supporting a 3-wire serial bus you should always find out what it means: standard 4-wire SPI, without the chip select pin from that count, since most buses use chip selects but only three wires carry "real" signals; (More, sometimes with an unshared SPI bus segment the device's chip select will be hard-wired as "always selected".) "real" 3-wire SPI; or even a RS232 cable with RXD, TXD, and shield/ground, or an application-specific signaling scheme.

Multi I/O SPI

As opposed to 3-wire serial buses, multi I/O SPI uses multiple parallel data lines (e.g. IO0 to IO3) to increase throughput. Dual I/O SPI using two data lines has comparable throughput to fast single I/O (MISO/MOSI). Quad I/O SPI using four data lines has approximately double the throughput. Multi I/O SPI devices tend to be half duplex similar to 3-Wire devices to avoid adding too many pins. These serial memory devices combine the advantage of more speed with reduced pin count as compared to parallel memory.

See also

  • Related Buses
  • Related Connectors
    • Secure Digital
      Secure Digital
      Secure Digital is a non-volatile memory card format developed by the SD Card Association for use in portable devices. The SD technology is used by more than 400 brands across dozens of product categories and more than 8,000 models, and is considered the de-facto industry standard.Secure Digital...

       - SD, SDHC, SDXC cards.
    • UEXT
      UEXT
      Univeral EXTension is a connector layout which includes power and three serials buses: Asynchronous, I2C, SPI. The connector layout was specified by Olimex Ltd and declared an open-project that is royalty-free.-Physical characteristics:...

       Connector.
  • Universal Metering Interface
    Universal Metering Interface
    UMI is a set of 3 free open specifications for smart metering and smart home products. The UMI specifications define; a module interface based on SPI, an optical communications interface based on EN62056-21 and a security interface based on ECC-256 and AES-128...

     (UMI)

External links

The source of this article is wikipedia, the free encyclopedia.  The text of this article is licensed under the GFDL.
 
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