Peripheral Component Interconnect

Peripheral Component Interconnect

Overview
Conventional PCI is a computer bus
Computer bus
In computer architecture, a bus is a subsystem that transfers data between components inside a computer, or between computers.Early computer buses were literally parallel electrical wires with multiple connections, but the term is now used for any physical arrangement that provides the same...

 for attaching hardware devices
Computer hardware
Personal computer hardware are component devices which are typically installed into or peripheral to a computer case to create a personal computer upon which system software is installed including a firmware interface such as a BIOS and an operating system which supports application software that...

 in a computer
Computer
A computer is a programmable machine designed to sequentially and automatically carry out a sequence of arithmetic or logical operations. The particular sequence of operations can be changed readily, allowing the computer to solve more than one kind of problem...

. These devices can take either the form of an integrated circuit
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...

 fitted onto the motherboard itself, called a planar device in the PCI specification, or an expansion card
Expansion card
The expansion card in computing is a printed circuit board that can be inserted into an expansion slot of a computer motherboard or backplane to add functionality to a computer system via the expansion bus.One edge of the expansion card holds the contacts that fit exactly into the slot...

 that fits into a slot. The PCI Local Bus was first implemented in IBM PC compatible
IBM PC compatible
IBM PC compatible computers are those generally similar to the original IBM PC, XT, and AT. Such computers used to be referred to as PC clones, or IBM clones since they almost exactly duplicated all the significant features of the PC architecture, facilitated by various manufacturers' ability to...

s, where it displaced the combination of ISA
Industry Standard Architecture
Industry Standard Architecture is a computer bus standard for IBM PC compatible computers introduced with the IBM Personal Computer to support its Intel 8088 microprocessor's 8-bit external data bus and extended to 16 bits for the IBM Personal Computer/AT's Intel 80286 processor...

 plus one VESA Local Bus
VESA Local Bus
The VESA Local Bus was mostly used in personal computers. VESA Local Bus worked alongside the ISA bus; it acted as a high-speed conduit for memory-mapped I/O and DMA, while the ISA bus handled interrupts and port-mapped I/O.-Historical overview:In the early 1990s, the I/O bandwidth of...

 as the bus configuration. It has subsequently been adopted for other computer types.
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Encyclopedia
Conventional PCI is a computer bus
Computer bus
In computer architecture, a bus is a subsystem that transfers data between components inside a computer, or between computers.Early computer buses were literally parallel electrical wires with multiple connections, but the term is now used for any physical arrangement that provides the same...

 for attaching hardware devices
Computer hardware
Personal computer hardware are component devices which are typically installed into or peripheral to a computer case to create a personal computer upon which system software is installed including a firmware interface such as a BIOS and an operating system which supports application software that...

 in a computer
Computer
A computer is a programmable machine designed to sequentially and automatically carry out a sequence of arithmetic or logical operations. The particular sequence of operations can be changed readily, allowing the computer to solve more than one kind of problem...

. These devices can take either the form of an integrated circuit
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...

 fitted onto the motherboard itself, called a planar device in the PCI specification, or an expansion card
Expansion card
The expansion card in computing is a printed circuit board that can be inserted into an expansion slot of a computer motherboard or backplane to add functionality to a computer system via the expansion bus.One edge of the expansion card holds the contacts that fit exactly into the slot...

 that fits into a slot. The PCI Local Bus was first implemented in IBM PC compatible
IBM PC compatible
IBM PC compatible computers are those generally similar to the original IBM PC, XT, and AT. Such computers used to be referred to as PC clones, or IBM clones since they almost exactly duplicated all the significant features of the PC architecture, facilitated by various manufacturers' ability to...

s, where it displaced the combination of ISA
Industry Standard Architecture
Industry Standard Architecture is a computer bus standard for IBM PC compatible computers introduced with the IBM Personal Computer to support its Intel 8088 microprocessor's 8-bit external data bus and extended to 16 bits for the IBM Personal Computer/AT's Intel 80286 processor...

 plus one VESA Local Bus
VESA Local Bus
The VESA Local Bus was mostly used in personal computers. VESA Local Bus worked alongside the ISA bus; it acted as a high-speed conduit for memory-mapped I/O and DMA, while the ISA bus handled interrupts and port-mapped I/O.-Historical overview:In the early 1990s, the I/O bandwidth of...

 as the bus configuration. It has subsequently been adopted for other computer types. PCI is being replaced by PCI-X
PCI-X
PCI-X, short for PCI-eXtended, is a computer bus and expansion card standard that enhances the 32-bit PCI Local Bus for higher bandwidth demanded by servers. It is a double-wide version of PCI, running at up to four times the clock speed, but is otherwise similar in electrical implementation and...

 and PCI Express
PCI Express
PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...

, but , most motherboards are still made with one or more PCI slots, which are sufficient for many uses.

The PCI specification covers the physical size of the bus (including the size and spacing of the circuit board edge electrical contacts), electrical characteristics, bus timing, and protocols. The specification can be purchased from the PCI Special Interest Group
PCI-SIG
The PCI-SIG or Peripheral Component Interconnect Special Interest Group is an electronics industry consortium responsible for specifying the Peripheral Component Interconnect , PCI-X, and PCI Express computer buses....

 (PCI-SIG).

Typical PCI cards used in PCs include: network card
Network card
A network interface controller is a computer hardware component that connects a computer to a computer network....

s, sound card
Sound card
A sound card is an internal computer expansion card that facilitates the input and output of audio signals to and from a computer under control of computer programs. The term sound card is also applied to external audio interfaces that use software to generate sound, as opposed to using hardware...

s, modem
Modem
A modem is a device that modulates an analog carrier signal to encode digital information, and also demodulates such a carrier signal to decode the transmitted information. The goal is to produce a signal that can be transmitted easily and decoded to reproduce the original digital data...

s, extra ports such as USB
Universal Serial Bus
USB is an industry standard developed in the mid-1990s that defines the cables, connectors and protocols used in a bus for connection, communication and power supply between computers and electronic devices....

 or serial
Serial port
In computing, a serial port is a serial communication physical interface through which information transfers in or out one bit at a time...

, TV tuner card
TV tuner card
A TV tuner card is a kind of television tuner that allows television signals to be received by a computer. Most TV tuners also function as video capture cards, allowing them to record television programs onto a hard disk much like the Tivo digital video recorder does.-Variants: The interfaces for...

s and disk controller
Disk controller
The disk controller is the circuit which enables the CPU to communicate with a hard disk, floppy disk or other kind of disk drive.Early disk controllers were identified by their storage methods and data encoding. They were typically implemented on a separate controller card...

s. PCI video card
Video card
A video card, Graphics Card, or Graphics adapter is an expansion card which generates output images to a display. Most video cards offer various functions such as accelerated rendering of 3D scenes and 2D graphics, MPEG-2/MPEG-4 decoding, TV output, or the ability to connect multiple monitors...

s replaced ISA and VESA cards, until growing bandwidth requirements outgrew the capabilities of PCI; the preferred interface for video cards became AGP
Accelerated Graphics Port
The Accelerated Graphics Port is a high-speed point-to-point channel for attaching a video card to a computer's motherboard, primarily to assist in the acceleration of 3D computer graphics. Since 2004 AGP has been progressively phased out in favor of PCI Express...

, and then PCI Express. PCI video cards remain available for use with old PCs without AGP
Accelerated Graphics Port
The Accelerated Graphics Port is a high-speed point-to-point channel for attaching a video card to a computer's motherboard, primarily to assist in the acceleration of 3D computer graphics. Since 2004 AGP has been progressively phased out in favor of PCI Express...

 or PCI Express slots.

Many devices previously provided on expansion cards are either commonly integrated onto motherboards, or more commonly available in USB and PCI Express versions. Modern PCs often have no cards fitted. However, PCI is still used for certain specialized cards.

History



Work on PCI began at Intel's Architecture Development Lab
Intel Architecture Labs
Intel Architecture Labs, also known as IAL, was the personal computer system research and development arm of Intel Corporation during the 1990s...

 circa 1990.

A team of Intel engineers (composed primarily of ADL engineers) defined the architecture and developed a proof of concept chipset and platform (Saturn) partnering with teams in the company's desktop PC systems and core logic product organizations. The original PCI architecture team included, among others, Dave Carson, Norm Rasmussen, Brad Hosler, Ed Solari, Bruce Young, Gary Solomon, Ali Oztaskin, Tom Sakoda, Rich Haslam, Jeff Rabe, and Steve Fischer.

PCI (Peripheral Component Interconnect) was immediately put to use in servers, replacing MCA
Micro Channel architecture
Micro Channel Architecture was a proprietary 16- or 32-bit parallel computer bus introduced by IBM in 1987 which was used on PS/2 and other computers through the mid 1990s.- Background :...

 and EISA
Extended Industry Standard Architecture
The Extended Industry Standard Architecture is a bus standard for IBM PC compatible computers...

 as the server expansion bus of choice. In mainstream PCs, PCI was slower to replace VESA Local Bus
VESA Local Bus
The VESA Local Bus was mostly used in personal computers. VESA Local Bus worked alongside the ISA bus; it acted as a high-speed conduit for memory-mapped I/O and DMA, while the ISA bus handled interrupts and port-mapped I/O.-Historical overview:In the early 1990s, the I/O bandwidth of...

 (VLB), and did not gain significant market penetration until late 1994 in second-generation Pentium PCs. By 1996 VLB was all but extinct, and manufacturers had adopted PCI even for 486
Intel 80486
The Intel 80486 microprocessor was a higher performance follow up on the Intel 80386. Introduced in 1989, it was the first tightly pipelined x86 design as well as the first x86 chip to use more than a million transistors, due to a large on-chip cache and an integrated floating point unit...

 computers. EISA continued to be used alongside PCI through 2000. Apple Computer
Apple Computer
Apple Inc. is an American multinational corporation that designs and markets consumer electronics, computer software, and personal computers. The company's best-known hardware products include the Macintosh line of computers, the iPod, the iPhone and the iPad...

 adopted PCI for professional Power Macintosh
Power Macintosh
Power Macintosh, later Power Mac, was a line of Apple Macintosh workstation-class personal computers based on various models of PowerPC microprocessors that were developed, marketed, and supported by Apple Inc. from March 1994 until August 2006. The first models were the Power Macintosh 6100,...

 computers (replacing NuBus
NuBus
NuBus is a 32-bit parallel computer bus, originally developed at MIT as a part of the NuMachine workstation project. The first complete implementation of the NuBus and the NuMachine was done by Western Digital for their NuMachine, and for the Lisp Machines Inc. LMI-Lambda. The NuBus was later...

) in mid-1995, and the consumer Performa
Macintosh Performa
The Macintosh Performa series was Apple Computer's consumer product family of Apple Macintosh personal computers sold through department stores and mass-market retailers from 1992 until 1997, when it was superseded by the Power Macintosh 5x00 series...

 product line (replacing LC PDS
Processor Direct Slot
Processor Direct Slot or PDS introduced by Apple Computer, in several of their Macintosh models, provided a limited measure of hardware expandibility, without going to the expense of providing full-fledged bus expansion slots.Typically, a machine would feature multiple bus expansions slots, if any...

) in mid-1996.

Later revisions of PCI added new features and performance improvements, including a 66 MHz 3.3 V
Volt
The volt is the SI derived unit for electric potential, electric potential difference, and electromotive force. The volt is named in honor of the Italian physicist Alessandro Volta , who invented the voltaic pile, possibly the first chemical battery.- Definition :A single volt is defined as the...

 standard and 133 MHz PCI-X
PCI-X
PCI-X, short for PCI-eXtended, is a computer bus and expansion card standard that enhances the 32-bit PCI Local Bus for higher bandwidth demanded by servers. It is a double-wide version of PCI, running at up to four times the clock speed, but is otherwise similar in electrical implementation and...

, and the adaptation of PCI signaling to other form factors. Both PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards.

The PCI-SIG introduced the serial PCI Express
PCI Express
PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...

 in 2004. At the same time they renamed PCI as Conventional PCI. Since then, motherboard manufacturers have included progressively fewer Conventional PCI slots in favor of the new standard.
PCI History
Spec Year Change Summary
PCI 1.0 1992 Original issue
PCI 2.0 1993 Incorporated connector and add-in card specification
PCI 2.1 1995 Incorporated clarifications and added 66 MHz chapter
PCI 2.2 1998 Incorporated ECN
Engineering Change Notice
An Engineering Change Notice , or Change Notice, is a document which records or authorises a change to a design. The reasons for the change should also be recorded....

s, and improved readability
PCI 2.3 2002 Incorporated ECNs, errata, and deleted 5 volt only keyed add-in cards
PCI 3.0 2002 Removed support for the 5.0 volt keyed system board connector

Auto configuration


PCI provides separate memory and I/O port address space
Address space
In computing, an address space defines a range of discrete addresses, each of which may correspond to a network host, peripheral device, disk sector, a memory cell or other logical or physical entity.- Overview :...

s for the x86 processor family, 64
64-bit
64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...

 and 32 bits
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....

, respectively. Addresses in these address spaces are assigned by software. A third address space, called the PCI Configuration Space
PCI Configuration Space
PCI configuration space is the underlying way that the Conventional PCI, PCI-X and PCI Express perform auto configuration of the cards inserted into their bus.- Technical information :...

, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or I/O
Input/output
In computing, input/output, or I/O, refers to the communication between an information processing system , and the outside world, possibly a human, or another information processing system. Inputs are the signals or data received by the system, and outputs are the signals or data sent from it...

 port space via its configuration space registers.

In a typical system, the firmware
Firmware
In electronic systems and computing, firmware is a term often used to denote the fixed, usually rather small, programs and/or data structures that internally control various electronic devices...

 (or operating system
Operating system
An operating system is a set of programs that manage computer hardware resources and provide common services for application software. The operating system is the most important type of system software in a computer system...

) queries all PCI buses at startup time (via PCI Configuration Space
PCI Configuration Space
PCI configuration space is the underlying way that the Conventional PCI, PCI-X and PCI Express perform auto configuration of the cards inserted into their bus.- Technical information :...

) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates the resources and tells each device what its allocation is.

The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.

Devices may have an on-board ROM
Read-only memory
Read-only memory is a class of storage medium used in computers and other electronic devices. Data stored in ROM cannot be modified, or can be modified only slowly or with difficulty, so it is mainly used to distribute firmware .In its strictest sense, ROM refers only...

 containing executable code for x86 or PA-RISC
PA-RISC family
PA-RISC is an instruction set architecture developed by Hewlett-Packard. As the name implies, it is a reduced instruction set computer architecture, where the PA stands for Precision Architecture...

 processors, an Open Firmware
Open Firmware
Open Firmware, or OpenBoot in Sun Microsystems parlance, is a standard defining the interfaces of a computer firmware system, formerly endorsed by the Institute of Electrical and Electronics Engineers . It originated at Sun, and has been used by Sun, Apple, IBM, and most other non-x86 PCI chipset...

 driver, or an EFI
Extensible Firmware Interface
The Unified Extensible Firmware Interface is a specification that defines a software interface between an operating system and platform firmware...

 driver. These are typically necessary for devices used during system startup, before device drivers are loaded by the operating system.

In addition there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly. "Fair" in this case means that devices won't use such a large portion of the available PCI bus bandwidth that other devices aren't able to get needed work done. Note, this does not apply to PCI Express.

Interrupts


Devices are required to follow a protocol so that the interrupt
Interrupt
In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....

 lines can be shared. The PCI bus includes four interrupt lines, all of which are available to each device. However, they are not wired in parallel as are the other PCI bus lines. The positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the one after that. Single-function devices use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines. This alleviates a common problem with sharing interrupts.

PCI bridges (between two PCI buses) map the four interrupt traces on each of their sides in varying ways. Some bridges use a fixed mapping, and in others it is configurable. In the general case, software cannot determine which interrupt line a device's INTA# pin is connected to across a bridge. The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is similarly implementation-dependent. The result is that it can be impossible to determine how a PCI device's interrupts will appear to software. Platform-specific BIOS code is meant to know this, and set a field in each device's configuration space indicating which IRQ it is connected to, but this process is unreliable.

PCI interrupt lines are level-triggered. This was chosen over edge-triggering in order to gain an advantage when servicing a shared interrupt line, and for robustness: edge triggered interrupts are easy to miss.

Later revisions of the PCI specification add support for message-signaled interrupts
Message Signaled Interrupts
Message Signaled Interrupts, in PCI 2.2and later in PCI Express, are an alternative way of generating an interrupt. Traditionally, a device has an interrupt pin which it asserts when it wants to interrupt the host CPU. While PCI Express does not have separate interrupt pins, it has special...

. In this system a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts. It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message signaling is in-band, it resolves some synchronization problems that can occur with posted writes and out-of-band interrupt lines.

PCI Express
PCI Express
PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...

 does not have physical interrupt lines at all. It uses message-signaled interrupts exclusively.

Conventional hardware specifications



These specifications represent the most common version of PCI used in normal PCs. clock
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...

 with synchronous
Synchronous circuit
A synchronous circuit is a digital circuit in which the parts are synchronized by a clock signal.In an ideal synchronous circuit, every change in the logical levels of its storage components is simultaneous. These transitions follow the level change of a special signal called the clock...

 transfers
  • Peak transfer rate of 133 MB
    Megabyte
    The megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: bytes generally for computer memory; and one million bytes generally for computer storage. The IEEE Standards Board has decided that "Mega will mean 1 000...

    /s (133 megabyte
    Megabyte
    The megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: bytes generally for computer memory; and one million bytes generally for computer storage. The IEEE Standards Board has decided that "Mega will mean 1 000...

    s per second) for 32-bit bus width (33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s)
  • 32-bit
    32-bit
    The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....

     bus width
  • 32- or 64-bit memory address space (4 gigabyte
    Gigabyte
    The gigabyte is a multiple of the unit byte for digital information storage. The prefix giga means 109 in the International System of Units , therefore 1 gigabyte is...

    s or 16 exabyte
    Exabyte
    The exabyte is a unit of information or computer storage equal to one quintillion bytes . The unit symbol for the exabyte is EB...

    s)
  • 32-bit I/O port space
  • 256-byte
    Byte
    The byte is a unit of digital information in computing and telecommunications that most commonly consists of eight bits. Historically, a byte was the number of bits used to encode a single character of text in a computer and for this reason it is the basic addressable element in many computer...

     (per device) configuration space
  • 5-volt signaling
  • Reflected-wave switching
    Reflected-wave switching
    Reflected-wave switching is a signalling technique used in backplane computer buses such as PCI.A backplane computer bus is a type of multilayer printed circuit board that has at least one solid layer of copper called the ground plane, and at least one layer of copper tracks that are used as wires...



The PCI specification also provides options for 3.3 V signaling, 64-bit
64-bit
64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...

 bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards.

The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master.

Card voltage and keying



Typical PCI cards have either one or two key notches, depending on their signaling voltage. Cards requiring 3.3 volts have a notch 56.21 mm from the card backplate; those requiring 5 volts have a notch 104.47 mm from the backplate. "Universal cards" accepting either voltage have both key notches. This allows cards to be fitted only into slots with a voltage they support.

Connector pinout


The PCI connector is defined as having 62 contacts on each side of the edge connector
Edge connector
An edge connector is the portion of a printed circuit board consisting of traces leading to the edge of the board that are intended to plug into a matching socket. The edge connector is a money-saving device because it only requires a single discrete female connector , and they also tend to be...

, but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side. Pin 1 is closest to the backplate. B and A sides are as follows, looking down into the motherboard connector.
32-bit PCI connector pinout
Pin Side B Side A Comments
1 −12V TRST# JTAG port pins (optional)
2 TCK +12V
3 Ground TMS
4 TDO TDI
5 +5V +5V
6 +5V INTA# Interrupt lines (open-drain)
7 INTB# INTC#
8 INTD# +5V
9 PRSNT1# Reserved Pulled low to indicate 7.5 or 25 W power required
10 Reserved IOPWR +5V or +3.3V
11 PRSNT2# Reserved Pulled low to indicate 7.5 or 15 W power required
12 Ground Ground Key notch for 3.3V-capable cards
13 Ground Ground
14 Reserved 3.3Vaux Standby power
Standby power
Standby power, also called vampire power, vampire draw, phantom load, or leaking electricity , refers to the electric power consumed by electronic and electrical appliances while they are switched off Standby power, also called vampire power, vampire draw, phantom load, or leaking electricity...

 (optional)
15 Ground RST# Bus reset
16 CLK IOPWR 33/66 MHz clock
17 Ground GNT# Bus grant from motherboard to card
18 REQ# Ground Bus request from card to motherboard
19 IOPWR PME# Power management event (optional) 3.3V, open drain, active low.
20 AD[31] AD[30] Address/data bus (upper half)
21 AD[29] +3.3V
22 Ground AD[28]
23 AD[27] AD[26]
24 AD[25] Ground
25 +3.3V AD[24]
26 C/BE[3]# IDSEL
27 AD[23] +3.3V
28 Ground AD[22]
29 AD[21] AD[20]
30 AD[19] Ground
31 +3.3V AD[18]
32 AD[17] AD[16]
33 C/BE[2]# +3.3V
34 Ground FRAME# Bus transfer in progress
35 IRDY# Ground Initiator ready
36 +3.3V TRDY# Target ready
37 DEVSEL# Ground Target selected
38 Ground STOP# Target requests halt
39 LOCK# +3.3V Locked transaction
40 PERR# SMBCLK SDONE Parity error; SMBus clock or Snoop done (obsolete)
41 +3.3V SMBDAT SBO# SMBus data or Snoop backoff (obsolete)
42 SERR# Ground System error
43 +3.3V PAR Even parity over AD[31:00] and C/BE[3:0]#
44 C/BE[1]# AD[15] Address/data bus (lower half)
45 AD[14] +3.3V
46 Ground AD[13]
47 AD[12] AD[11]
48 AD[10] Ground
49 M66EN Ground AD[09]
50 Ground Ground Key notch for 5V-capable cards
51 Ground Ground
52 AD[08] C/BE[0]# Address/data bus (lower half)
53 AD[07] +3.3V
54 +3.3V AD[06]
55 AD[05] AD[04]
56 AD[03] Ground
57 Ground AD[02]
58 AD[01] AD[00]
59 IOPWR IOPWR
60 ACK64# REQ64# For 64-bit extension; no connect for 32-bit devices.
61 +5V +5V
62 +5V +5V

64-bit PCI extends this by an additional 32 contacts on each side which provide AD[63:32], C/BE[7:4]#, the PAR64 parity signal, and a number of power and ground pins.
Legend
Ground pin Zero volt reference
Power pin Supplies power to the PCI card
Output pin Driven by the PCI card, received by the motherboard
Initiator output Driven by the master/initiator, received by the target
I/O signal May be driven by initiator or target, depending on operation
Target output Driven by the target, received by the initiator/master
Input Driven by the motherboard, received by the PCI card
Open drain May be pulled low and/or sensed by multiple cards
Reserved Not presently used, do not connect


Most lines are connected to each slot in parallel. The exceptions are:
  • Each slot has its own REQ# output to, and GNT# input from the motherboard arbiter.
  • Each slot has its own IDSEL line, usually connected to a specific AD line.
  • TDO is daisy-chained to the following slot's TDI. Cards without JTAG support must connect TDI to TDO so as not to break the chain.
  • PRSNT1# and PRSNT2# for each slot have their own pull-up resistors on the motherboard. The motherboard may (but does not have to) sense these pins to determine the presence of PCI cards and their power requirements.
  • REQ64# and ACK64# are individually pulled up on 32-bit only slots.
  • The interrupt lines INTA# through INTD# are connected to all slots in different orders. (INTA# on one slot is INTB# on the next and INTC# on the one after that.)


Notes:
  • IOPWR is +3.3V or +5V, depending on the backplane. The slots also have a ridge in one of two places which prevents insertion of cards that do not have the corresponding key notch, indicating support for that voltage standard. Universal cards have both key notches and use IOPWR to determine their I/O signal levels.
  • The PCI SIG strongly encourages 3.3 V PCI signaling, requiring support for it since standard revision 2.3, but most PC motherboards use the 5 V variant. Thus, while many currently available PCI cards support both, and have two key notches to indicate that, there are still a large number of 5 V-only cards on the market.
  • The M66EN pin is an additional ground on 5V PCI busses found in most PC motherboards. Cards and motherboards that do not support 66 MHz operation also ground this pin. If all participants support 66 MHz operation, a pull-up resistor on the motherboard raises this signal high and 66 MHz operation is enabled.
  • At least one of PRSNT1# and PRSNT2# must be grounded by the card. The combination chosen indicates the total power requirements of the card (25 W, 15 W, or 7.5 W).
  • SBO# and SDONE are signals from a cache controller to the current target. They are not initiator outputs, but are colored that way because they are target inputs.

Full-size card


The original "full-size" PCI card is specified as a height of 107 mm (4.2 inches) and a depth of 312 mm (12.283 inches). The height includes the edge card connector. However, most modern PCI cards are half-length or smaller (see below) and many modern PCs cannot fit a full-size card.

Card backplate


In addition to these dimensions the physical size and location of a card's backplate are also standardized. The backplate is the part that fastens to the card cage to stabilize the card and also contains external connectors, so it usually attaches in a window so it is accessible from outside the computer case. The backplate is fixed to the cage by a 6-32 screw
Computer case screws
Computer case screws are the hardware used to fasten together parts of a computer case and to fasten the system components to the case. Although there are numerous manufacturers of computer cases throughout the world, the computer industry has generally standardized on some specific screw thread...

.

The card itself can be a smaller size, but the backplate must still be full-size and properly located so that the card fits in any standard PCI slot.

Half-length extension card (de-facto standard)


This is in fact the practical standard now – the majority of modern PCI cards fit inside this length.
  • Width: 0.6 inches (15.24 mm)
  • Depth: 6.9 inches (175.26 mm)
  • Height: 4.2 inches (106.68 mm)

Low-profile (half-height) card


The PCI organization has defined a standard for "low-profile" cards, which basically fit in the following ranges:
  • Height: 1.42 inches (36.07 mm) to 2.536 inches (64.41 mm)
  • Depth: 4.721 inches (119.91 mm) to 6.6 inches (167.64 mm)

The bracket is also reduced in height, to a standard 3.118 inches (79.2 mm). The smaller bracket will not fit a standard PC case, but will fit in a 2U rack-mount
Rack unit
A rack unit or U is a unit of measure used to describe the height of equipment intended for mounting in a 19-inch rack or a 23-inch rack...

 case. Many manufacturers supply both types of bracket (brackets are typically screwed to the card so changing them is not difficult).

These cards may be known by other names such as "slim".

Mini PCI


Mini PCI was added to PCI version 2.2 for use in laptop
Laptop
A laptop, also called a notebook, is a personal computer for mobile use. A laptop integrates most of the typical components of a desktop computer, including a display, a keyboard, a pointing device and speakers into a single unit...

s; it uses a 32-bit, 33 MHz bus with powered connections (3.3 V only; 5 V is limited to 100 mA) and support for bus mastering
Bus mastering
In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate transactions...

 and DMA
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....

. The standard size for Mini PCI cards is approximately a quarter of their full-sized counterparts. As there is no access to the card from outside the case, unlike desktop PCI cards with brackets carrying connectors, there are limitations on the functions they may perform.

Many Mini PCI devices were developed such as Wi-Fi
Wi-Fi
Wi-Fi or Wifi, is a mechanism for wirelessly connecting electronic devices. A device enabled with Wi-Fi, such as a personal computer, video game console, smartphone, or digital audio player, can connect to the Internet via a wireless network access point. An access point has a range of about 20...

, Fast Ethernet
Fast Ethernet
In computer networking, Fast Ethernet is a collective term for a number of Ethernet standards that carry traffic at the nominal rate of 100 Mbit/s, against the original Ethernet speed of 10 Mbit/s. Of the fast Ethernet standards 100BASE-TX is by far the most common and is supported by the...

, Bluetooth
Bluetooth
Bluetooth is a proprietary open wireless technology standard for exchanging data over short distances from fixed and mobile devices, creating personal area networks with high levels of security...

, modem
Modem
A modem is a device that modulates an analog carrier signal to encode digital information, and also demodulates such a carrier signal to decode the transmitted information. The goal is to produce a signal that can be transmitted easily and decoded to reproduce the original digital data...

s (often Winmodems
Softmodem
A Softmodem, or software modem, is a modem with minimal hardware capacities, designed to use a host computer's resources to perform most of the tasks performed by dedicated hardware in a traditional modem.A Softmodem is also referred to as a Winmodem because the first commercially available...

), sound card
Sound card
A sound card is an internal computer expansion card that facilitates the input and output of audio signals to and from a computer under control of computer programs. The term sound card is also applied to external audio interfaces that use software to generate sound, as opposed to using hardware...

s, cryptographic accelerator
Cryptographic accelerator
A cryptographic accelerator is a device that performs processor-intensive decrypting/encrypting while freeing the host CPU to perform other tasks. In general cryptographic accelerator is a co-processor. Common use for cryptographic accelerator is a webserver protecting data transmitted through...

s, SCSI
SCSI
Small Computer System Interface is a set of standards for physically connecting and transferring data between computers and peripheral devices. The SCSI standards define commands, protocols, and electrical and optical interfaces. SCSI is most commonly used for hard disks and tape drives, but it...

, IDE–ATA
AT Attachment
Parallel ATA , originally ATA, is an interface standard for the connection of storage devices such as hard disks, solid-state drives, floppy drives, and optical disc drives in computers. The standard is maintained by X3/INCITS committee...

, SATA
Sata
Sata is a traditional dish from the Malaysian state of Terengganu, consisting of spiced fish meat wrapped in banana leaves and cooked on a grill.It is a type of Malaysian fish cake, or otak-otak...

 controllers and combination cards. Mini PCI cards can be used with regular PCI-equipped hardware, using Mini PCI-to-PCI converters. Mini PCI has been superseded by the much narrower PCI Express Mini Card.

Technical details of Mini PCI


Mini PCI cards have a 2 W maximum power consumption, which limits the functionality that can be implemented in this form factor. They also are required to support the CLKRUN# PCI signal used to start and stop the PCI clock for power management purposes.

There are three card form factors: Type I, Type II, and Type III cards. The card connector used for each type include: Type I and II use a 100-pin stacking connector, while Type III uses a 124-pin edge connector, i.e. the connector for Types I and II differs from that for Type III, where the connector is on the edge of a card, like with a SO-DIMM
SO-DIMM
A SO-DIMM, or small outline dual in-line memory module, is a type of computer memory built using integrated circuits.SO-DIMMs are a smaller alternative to a DIMM, being roughly half the size of regular DIMMs...

. The additional 24 pins provide the extra signals required to route I/O
Input/output
In computing, input/output, or I/O, refers to the communication between an information processing system , and the outside world, possibly a human, or another information processing system. Inputs are the signals or data received by the system, and outputs are the signals or data sent from it...

 back through the system connector (audio, AC-Link, LAN
Län
Län and lääni refer to the administrative divisions used in Sweden and previously in Finland. The provinces of Finland were abolished on January 1, 2010....

, phone-line interface). Type II cards have RJ11 and RJ45 mounted connectors. These cards must be located at the edge of the computer or docking station so that the RJ11 and RJ45 ports can be mounted for external access.
Type Card on outer edge of host system Connector Size Comments
IA No 100-Pin Stacking 7.5 × 70 × 45 mm Large Z dimension (7.5 mm)
IB No 100-Pin Stacking 5.5 × 70 × 45 mm Smaller Z dimension (5.5 mm)
IIA Yes 100-Pin Stacking 17.44 × 70 × 45 mm Large Z dimension (17.44 mm)
IIB Yes 100-Pin Stacking 5.5 × 78 × 45 mm Smaller Z dimension (5.5 mm)
IIIA No 124-Pin Card Edge 2.4 × 59.6 × 50.95 mm Larger Y dimension (50.95 mm)
IIIB No 124-Pin Card Edge 2.4 × 59.6 × 44.6 mm Smaller Y dimension (44.6 mm)


Mini PCI is distinct from 144-pin Micro PCI.

PC/104-Plus and PCI-104


The PC/104
PC/104
PC/104 is an embedded computer standard controlled by the which defines both a form factor and computer bus. PC/104 is intended for specialized embedded computing environments where applications depend on reliable data acquisition despite an often extreme environment...

-Plus and PCI-104 embedded form factors include a stacking 120 pin PCI connector.

Other physical variations


Typically consumer systems specify "N × PCI slots" without specifying actual dimensions of the space available. In some small-form-factor systems, this may not be sufficient to allow even "half-length" PCI cards to fit. Despite this limitation, these systems are still useful because many modern PCI cards are considerably smaller than half-length.

PCI bus transactions


PCI bus traffic consists of a series of PCI bus transactions. Each transaction consists of an address phase followed by one or more data phases. The direction of the data phases may be from initiator to target (write transaction) or vice-versa (read transaction), but all of the data phases must be in the same direction. Either party may pause or halt the data phases at any point. (One common example is a low-performance PCI device that does not support burst transactions, and always halts a transaction after the first data phase.)

Any PCI device may initiate a transaction. First, it must request permission from a PCI bus arbiter on the motherboard. The arbiter grants permission to one of the requesting devices. The initiator begins the address phase by broadcasting a 32-bit address plus a 4-bit command code, then waits for a target to respond. All other devices examine this address and one of them responds a few cycles later.

64-bit addressing is done using a two-stage address phase. The initiator broadcasts the low 32 address bits, accompanied by a special "dual address cycle" command code. Devices which do not support 64-bit addressing can simply not respond to that command code. The next cycle, the initiator transmits the high 32 address bits, plus the real command code. The transaction operates identically from that point on. To ensure compatibility with 32-bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order address bits are all zero.

While the PCI bus transfers 32 bits per data phase, the initiator transmits a 4 byte enable signals indicating which 8-bit bytes are to be considered significant. In particular, a write must affect only the enabled bytes in the target PCI device. They are of little importance for memory reads, but I/O reads might have side effects. The PCI standard explicitly allows a data phase with no bytes enabled, which must behave as a no-op.

PCI address spaces


PCI has three address spaces: memory, I/O address, and configuration.

Memory addresses are 32 bits (optionally 64 bits) in size, support caching
Cache
In computer engineering, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere...

 and can be burst transactions.

I/O addresses are for compatibility with the Intel x86 architecture
X86 architecture
The term x86 refers to a family of instruction set architectures based on the Intel 8086 CPU. The 8086 was launched in 1978 as a fully 16-bit extension of Intel's 8-bit based 8080 microprocessor and also introduced segmentation to overcome the 16-bit addressing barrier of such designs...

's I/O port address space. Although the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O.

Finally, PCI configuration space
PCI Configuration Space
PCI configuration space is the underlying way that the Conventional PCI, PCI-X and PCI Express perform auto configuration of the cards inserted into their bus.- Technical information :...

 provides access to 256 bytes of special configuration registers per PCI device. Each PCI slot gets its own configuration space address range. The registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators. When a computer is first turned on, all PCI devices respond only to their configuration space accesses. The computers BIOS scans for devices and assigns Memory and I/O address ranges to them.

If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation. In case of reads, it is customary to supply all-ones for the read data value (0xFFFFFFFF) in this case. PCI devices therefore generally attempt to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.

PCI command codes


There are 16 possible 4-bit command codes, and 12 of them are assigned. With the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read (data sent from target to initiator) or a write (data sent from an initiator to target). PCI targets must examine the command code as well as the address and not respond to address phases which specify an unsupported command code.

The commands that refer to cache lines depend on the PCI configuration space
PCI Configuration Space
PCI configuration space is the underlying way that the Conventional PCI, PCI-X and PCI Express perform auto configuration of the cards inserted into their bus.- Technical information :...

 cache line size register being set up properly; they may not be used until that has been done.

0000: Interrupt Acknowledge
This is a special form of read cycle implicitly addressed to the interrupt controller, which returns an interrupt vector. The 32-bit address field is ignored. One possible implementation is to generate an interrupt acknowledge cycle on an ISA bus using a PCI/ISA bus bridge. This command is for IBM PC compatibility
IBM PC compatible
IBM PC compatible computers are those generally similar to the original IBM PC, XT, and AT. Such computers used to be referred to as PC clones, or IBM clones since they almost exactly duplicated all the significant features of the PC architecture, facilitated by various manufacturers' ability to...

; if there is no Intel 8259
Intel 8259
The Intel 8259 is a Programmable Interrupt Controller designed for the Intel 8085 and Intel 8086 microprocessors. The initial part was 8259, a later A suffix version was upward compatible and usable with the 8086 or 8088 processor...

 style interrupt controller on the PCI bus, this cycle need never be used.


0001: Special Cycle
This cycle is a special broadcast write of system events that PCI card may be interested in. The address field of a special cycle is ignored, but it is followed by a data phase containing a payload message. The currently defined messages announce that the processor is stopping for some reason (e.g. to save power). No device ever responds to this cycle; it is always terminated with a master abort after leaving the data on the bus for at least 4 cycles.


0010: I/O Read
This performs a read from I/O space. All 32 bits of the read address are provided, so that a device can (for compatibility reasons) implement less than 4 bytes worth of I/O registers. If the byte enables request data not within the address range supported by the PCI device (e.g. a 4-byte read from a device which only supports 2 bytes of I/O address space), it must be terminated with a target abort. Multiple data cycles are permitted, using linear (simple incrementing) burst ordering.
The PCI standard is discouraging the use of I/O space in new devices, preferring that as much as possible be done through main memory mapping.


0011: I/O Write
This performs a write to I/O space.


010x: Reserved
A PCI device must not respond to an address cycle with these command codes.


0110: Memory Read
This performs a read cycle from memory space. Because the smallest memory space a PCI device is permitted to implement is 16 bits, the two least significant bits of the address are not needed; equivalent information will arrive in the form of byte select signals. They instead specify the order in which burst data must be returned. If a device does not support the requested order, it must provide the first word and then disconnect.
If a memory space is marked as "prefetchable", then the target device must ignore the byte select signals on a memory read and always return 32 valid bits.


0111: Memory Write
This operates similarly to a memory read. The byte select signals are more important in a write, as unselected bytes must not be written to memory.
Generally, PCI writes are faster than PCI reads, because a device can buffer the incoming write data and release the bus faster. For a read, it must delay the data phase until the data has been fetched.


100x: Reserved
A PCI device must not respond to an address cycle with these command codes.


1010: Configuration Read
This is similar to an I/O read, but reads from PCI configuration space. A device must respond only if the low 11 bits of the address specify a function and register that it implements, and if the special IDSEL signal is asserted. It must ignore the high 21 bits. Burst reads (using linear incrementing) are permitted in PCI configuration space.
Unlike I/O space, standard PCI configuration registers are defined so that reads never disturb the state of the device. It is possible for a device to have configuration space registers beyond the standard 64 bytes which have read side effects, but this is rare.
Configuration space accesses often have a few cycles of delay in order to allow the IDSEL lines to stabilize, which makes them slower than other forms of access. Also, a configuration space access requires a multi-step operation rather than a single machine instruction. Thus, it is best to avoid them during routine operation of a PCI device.


1011: Configuration Write
This operates analogously to a configuration read.


1100: Memory Read Multiple
This command is identical to a generic memory read, but includes the hint that a long read burst will continue beyond the end of the current cache line, and the target should internally prefetch a large amount of data. A target is always permitted to consider this a synonym for a generic memory read.


1101: Dual Address Cycle
When accessing a memory address that requires more than 32 bits to represent, the address phase begins with this command and the low 32 bits of the address, followed by a second cycle with the actual command and the high 32 bits of the address. PCI targets that do not support 64-bit addressing can simply treat this as another reserved command code and not respond to it. This command code can only be used with a non-zero high-order address word; it is forbidden to use this cycle if not necessary.


1110: Memory Read Line
This command is identical to a generic memory read, but includes the hint that the read will continue to the end of the cache line. A target is always permitted to consider this a synonym for a generic memory read.


1111: Memory Write and Invalidate
This command is identical to a generic memory write, but comes with the guarantee that one or more whole cache lines will be written, with all byte selects enabled. This is an optimization for write-back caches snooping the bus. Normally, a write-back cache holding dirty data must interrupt the write operation long enough write its own dirty data first. If the write is performed using this command, the data to be written back is guaranteed to be irrelevant, and can simply be invalidated in the write-back cache.
This optimization only affects the snooping cache, and makes no difference to the target, which may treat this as a synonym for the memory write command.

PCI bus latency


Soon after promulgation of the PCI specification, it was discovered that lengthy transactions by some devices, due to slow acknowledgments, long data bursts, or some combination, could cause buffer underrun
Buffer underrun
In computing, buffer underrun or buffer underflow is a state occurring when a buffer used to communicate between two devices or processes is fed with data at a lower speed than the data is being read from it. This requires the program or device reading from the buffer to pause its processing while...

 or overrun in other devices. Recommendations on the timing of individual phases in Revision 2.0 were made mandatory in revision 2.1:
  • A target must be able to complete the initial data phase (assert TRDY# and/or STOP#) within 16 cycles of the start of a transaction.
  • An initiator must complete each data phase (assert IRDY#) within 8 cycles.

Additionally, as of revision 2,1, all initiators capable of bursting more than 2 data phases must implement a programmable latency timer. The timer starts counting clock cycles when a transaction starts (initiator asserts FRAME#). If the timer has expired and the arbiter has removed GNT#, then the initiator must terminate the transaction at the next legal opportunity. This is usually the next data phase, but Memory Write and Invalidate transactions must continue to the end of the cache line.

Delayed transactions


Devices unable to meet those timing restrictions must use a combination of posted writes (for memory writes) and delayed transactions (for other writes and all reads). In a delayed transaction, the target records the transaction (including the write data) internally and aborts (asserts STOP# rather than TRDY#) the first data phase. The initiator must retry exactly the same transaction later. In the interim, the target internally performs the transaction, and waits for the retried transaction. When the retried transaction is seen, the buffered result is delivered.

A device may be the target of other transactions while completing one delayed transaction; it must remember the transaction type, address, byte selects and (if a write) data value, and only complete the correct transaction.

If the target has a limit on the number of delayed transactions that it can record internally (simple targets may impose a limit of 1), it will force those transactions to retry without recording them. They will be dealt with when the current delayed transaction is completed. If two initiators attempt the same transaction, a delayed transaction begun by one may have its result delivered to the other; this is harmless.

A target abandons a delayed transaction when a retry succeeds in delivering the buffered result, the bus is reset, or when 215=32768 clock cycles (approximately 1 ms) elapse without seeing a retry. The latter should never happen in normal operation, but it prevents a deadlock
Deadlock
A deadlock is a situation where in two or more competing actions are each waiting for the other to finish, and thus neither ever does. It is often seen in a paradox like the "chicken or the egg"...

 of the whole bus if one initiator is reset or malfunctions.

PCI bus bridges


The PCI standard permits multiple independent PCI busses to be connected by bus bridges that will forward operations on one bus to another when required. Although conventional PCI tends not to use many bus bridges, PCI express systems use many; each PCI express slot appears to be a separate bus, connected by a bridge to the others.

Posted writes


Generally, when a bus bridge sees a transaction on one bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready. One notable exception occurs in the case of memory writes. Here, the bridge may record the write data internally (if it has room) and signal completion of the write before the forwarded write has completed. Or, indeed, before it has begun. Such "sent but not yet arrived" writes are referred to as "posted writes", by analogy with a postal mail message. Although they offer great opportunity for performance gains, the rules governing what is permissible are somewhat intricate.

Combining, merging, and collapsing


The PCI standard permits bus bridges to convert multiple bus transactions into one larger transaction under certain situations. This can improve the efficiency of the PCI bus.
Combining : Write transactions to consecutive addresses may be combined into a longer burst write, as long as the order of the accesses in the burst is the same as the order of the original writes. It is permissible to insert extra data phases with all byte enables turned off if the writes are almost consecutive.
Merging : Multiple writes to disjoint portions of the same word may be merged together into a single write with multiple byte enables asserted. In this case, writes were presented to the bus bridge in a particular order are merged so they occur at the same time when forwarded.
Collapsing : Multiple writes to the same byte or bytes may not be combined, for example, by performing only the second write and skipping the first write that was overwritten. This is because the PCI specification permits writes to have side effects.

PCI bus signals


PCI bus transactions are controlled by five main control signals, two driven by the initiator of a transaction (FRAME# and IRDY#), and three driven by the target (DEVSEL#, TRDY#, and STOP#). There are two additional arbitration signals (REQ# and GNT#) which are used to obtain permission to initiate a transaction. All are active-low, meaning that the active or asserted state is a low voltage
Voltage
Voltage, otherwise known as electrical potential difference or electric tension is the difference in electric potential between two points — or the difference in electric potential energy per unit charge between two points...

. Pull-up resistors on the motherboard ensure they will remain high (inactive or deasserted) if not driven by any device, but the PCI bus does not depend on the resistors to change the signal level; all devices drive the signals high for one cycle before ceasing to drive
Three-state logic
In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit...

 the signals.

Signal timing


All PCI bus signals are sampled on the rising edge of the clock. Signals nominally change on the falling edge of the clock, giving each PCI device approximately one half a clock cycle to decide how to respond to the signals it observed on the rising edge, and one half a clock cycle to transmit its response to the other device.

The PCI bus requires that every time the device driving a PCI bus signal changes, one turnaround cycle must elapse between the time the one device stops driving the signal and the other device starts. Without this, there might be a period when both devices were driving the signal, which would interfere with bus operation.

The combination of this turnaround cycle and the requirement to drive a control line high for one cycle before ceasing to drive it means that each of the main control lines must be high for a minimum of two cycles when changing owners. The PCI bus protocol is designed so this is rarely a limitation; only in a few special cases (notably fast back-to-back transactions) is it necessary to insert additional delay to meet this requirement.

Arbitration


Any device on a PCI bus that is capable of acting as a bus master may initiate a transaction with any other device. To ensure that only one transaction is initiated at a time, each master must first wait for a bus grant signal, GNT#, from an arbiter located on the motherboard. Each device has a separate request line REQ# that requests the bus, but the arbiter may "park" the bus grant signal at any device if there are no current requests.

The arbiter may remove GNT# at any time. A device which loses GNT# may complete its current transaction, but may not start one (by asserting FRAME#) unless it observes GNT# asserted the cycle before it begins.

The arbiter may also provide GNT# at any time, including during another master's transaction. During a transaction, either FRAME# or IRDY# or both are asserted; when both are deasserted, the bus is idle. A device may initiate a transaction at any time that GNT# is asserted and the bus is idle.

Address phase


A PCI bus transaction begins with an address phase. The initiator, seeing that it has GNT# and the bus is idle, drives the target address onto the AD[31:0] lines, the associated command (e.g. memory read, or I/O write) on the C/BE[3:0]# lines, and pulls FRAME# low.

Each other device examines the address and command and decides whether to respond as the target by asserting DEVSEL#. A device must respond by asserting DEVSEL# within 3 cycles. Devices which promise to respond within 1 or 2 cycles are said to have "fast DEVSEL" or "medium DEVSEL", respectively. (Actually, the time to respond is 2.5 cycles, since PCI devices must transmit all signals half a cycle early so that they can be received three cycles later.)

Note that a device must latch the address on the first cycle; the initiator is required to remove the address and command from the bus on the following cycle, even before receiving a DEVSEL# response. The additional time is available only for interpreting the address and command after it is captured.

On the fifth cycle of the address phase (or earlier if all other devices have medium DEVSEL or faster), a catch-all "subtractive decoding" is allowed for some address ranges. This is commonly used by an ISA bus bridge for addresses within its range (24 bits for memory and 16 bits for I/O).

On the sixth cycle, if there has been no response, the initiator may abort the transaction by deasserting FRAME#. This is known as master abort termination and it is customary for PCI bus bridges to return all-ones data (0xFFFFFFFF) in this case. PCI devices therefore are generally designed to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.

Address phase timing



_ 0_ 1_ 2_ 3_ 4_ 5_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/
___
GNT# \___/XXXXXXXXXXXXXXXXXXX (GNT# Irrelevant after cycle has started)
_______
FRAME# \___________________
___
AD[31:0] -------<___>--------------- (Address only valid for one cycle.)
___ _______________
C/BE[3:0]# -------<___X_______________ (Command, then first data phase byte enables)
_______________________
DEVSEL# \___\___\___\___
Fast Med Slow Subtractive
_ _ _ _ _ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/
0 1 2 3 4 5


On the rising edge of clock 0, the initiator observes FRAME# and IRDY# both high, and GNT# low, so it drives the address, command, and asserts FRAME# in time for the rising edge of clock 1. Targets latch the address and begin decoding it. They may respond with DEVSEL# in time for clock 2 (fast DEVSEL), 3 (medium) or 4 (slow). Subtractive decode devices, seeing no other response by clock 4, may respond on clock 5. If the master does not see a response by clock 5, it will terminate the transaction and remove FRAME# on clock 6.

TRDY# and STOP# are deasserted (high) during the address phase. The initiator may assert IRDY# as soon as it is ready to transfer data, which could theoretically be as soon as clock 2.

Dual-cycle address


To allow 64-bit addressing, a master will present the address over two consecutive cycles. First, it sends the low-order address bits with a special "dual-cycle address" command on the C/BE[3:0]#. On the following cycle, it sends the high-order address bits and the actual command. Dual-address cycles are forbidden if the high-order address bits are zero, so devices which do not support 64-bit addressing can simply not respond to dual cycle commands.


_ 0_ 1_ 2_ 3_ 4_ 5_ 6_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
___
GNT# \___/XXXXXXXXXXXXXXXXXXXXXXX
_______
FRAME# \_______________________
___ ___
AD[31:0] -------<___X___>--------------- (Low, then high bits)
___ ___ _______________
C/BE[3:0]# -------<___X___X_______________ (DAC, then actual command)
___________________________
DEVSEL# \___\___\___\___
Fast Med Slow
_ _ _ _ _ _ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
0 1 2 3 4 5 6

Configuration access


Addresses for PCI configuration space access are decoded specially. For these, the low-order address lines specify the offset of the desired PCI configuration register, and the high-order address lines are ignored. Instead, an additional address signal, the IDSEL input, must be high before a device may assert DEVSEL#. Each slot connects a different high-order address line to the IDSEL pin, and is selected using one-hot encoding on the upper address lines.

Data phases


After the address phase (specifically, beginning with the cycle that DEVSEL# goes low) comes a burst of one or more data phases. In all cases, the initiator drives active-low byte select signals on the C/BE[3:0]# lines, but the data on the AD[31:0] may be driven by the initiator (in case of writes) or target (in case of reads).

During data phases, the C/BE[3:0]# lines are interpreted as active-low byte enables. In case of a write, the asserted signals indicate which of the four bytes on the AD bus are to be written to the addressed location. In the case of a read, they indicate which bytes the initiator is interested in. For reads, it is always legal to ignore the byte enable signals and simply return all 32 bits; cacheable memory resources are required to always return 32 valid bits. The byte enables are mainly useful for I/O space accesses where reads have side effects.

A data phase with all four C/BE# lines deasserted is explicitly permitted by the PCI standard, and must have no effect on the target (other than to advance the address in the burst access in progress).

The data phase continues until both parties are ready to complete the transfer and continue to the next data phase. The initiator asserts IRDY# (initiator ready) when it no longer needs to wait, while the target asserts TRDY# (target ready). Whichever side is providing the data must drive it on the AD bus before asserting its ready signal.

Once one of the participants asserts its ready signal, it may not become un-ready or otherwise alter its control signals until the end of the data phase. The data recipient must latch the AD bus each cycle until it sees both IRDY# and TRDY# asserted, which marks the end of the current data phase and indicates that the just-latched data is the word to be transferred.

To maintain full burst speed, the data sender then has half a clock cycle after seeing both IRDY# and TRDY# asserted to drive the next word onto the AD bus.


0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_ 9_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
___ _______ ___ ___ ___
AD[31:0] ---<___XXXXXXXXX_______XXXXX___X___X___ (If a write)
___ ___ _______ ___ ___
AD[31:0] ---<___>~~~ ___ _______________ _______ ___ ___
C/BE[3:0]# ---<___X_______________X_______X___X___ (Must always be valid)
_______________ | ___ | | |
IRDY# x \_______/ x \___________
___________________ | | | |
TRDY# x x \___________________
___________ | | | |
DEVSEL# \___________________________
___ | | | |
FRAME# \___________________________________
_ _ _ _ _ |_ _ |_ |_ |_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
0 1 2 3 4 5 6 7 8 9

This continues the address cycle illustrated above, assuming a single address cycle with medium DEVSEL, so the target responds in time for clock 3.
However, at that time, neither side is ready to transfer data. For clock 4, the initiator is ready, but the target is not. On clock 5, both are ready, and a data transfer takes place (as indicated by the vertical lines). For clock 6, the target is ready to transfer, but the initator is not. On clock 7, the initiator becomes ready, and data is transferred. For clocks 8 and 9, both sides remain ready to transfer data, and data is transferred at the maximum possible rate (32 bits per clock cycle).

In case of a read, clock 2 is reserved for turning around the AD bus, so the target is not permitted to drive data on the bus even if it is capable of fast DEVSEL.

Fast DEVSEL# on reads


A target that supports fast DEVSEL could in theory begin responding to a read the cycle after the address is presented. This cycle is, however, reserved for AD bus turnaround. Thus, a target may not drive the AD bus (and thus may not assert TRDY#) on the second cycle of a transaction. Note that most targets will not be this fast and will not need any special logic to enforce this condition.

Ending transactions


Either side may request that a burst end after the current data phase. Simple PCI devices that do not support multi-word bursts will always request this immediately. Even devices that do support bursts will have some limit on the maximum length they can support, such as the end of their addressable memory.

Initiator burst termination


The initiator can mark any data phase as the final one in a transaction by deasserting FRAME# at the same time as it asserts IRDY#. The cycle after the target asserts TRDY#, the final data transfer is complete, both sides deassert their respective RDY# signals, and the bus is idle again. The master may not deassert FRAME# before asserting IRDY#, nor may it deassert FRAME# while waiting, with IRDY# asserted, for the target to assert TRDY#.

The only minor exception is a master abort termination, when no target responds with DEVSEL#. Obviously, it is pointless to wait for TRDY# in such a case. However, even in this case, the master must assert IRDY# for at least one cycle after deasserting FRAME#. (Commonly, a master will assert IRDY# before receiving DEVSEL#, so it must simply hold IRDY# asserted for one cycle longer.) This is to ensure that bus turnaround timing rules are obeyed on the FRAME# line.

Target burst termination


The target requests the initiator end a burst by asserting STOP#. The initiator will then end the transaction by deasserting FRAME# at the next legal opportunity; if it wishes to transfer more data, it will continue in a separate transaction. There are several ways for the target to do this:
Disconnect with data
If the target asserts STOP# and TRDY# at the same time, this indicates that the target wishes this to be the last data phase. For example, a target that does not support burst transfers will always do this to force single-word PCI transactions. This is the most efficient way for a target to end a burst.

Disconnect without data
If the target asserts STOP# without asserting TRDY#, this indicates that the target wishes to stop without transferring data. STOP# is considered equivalent to TRDY# for the purpose of ending a data phase, but no data is transferred.

Retry
A Disconnect without data before transferring any data is a retry, and unlike other PCI transactions, PCI initiators are required to pause slightly before continuing the operation. See the PCI specification for details.

Target abort
Normally, a target holds DEVSEL# asserted through the last data phase. However, if a target deasserts DEVSEL# before disconnecting without data (asserting STOP#), this indicates a target abort, which is a fatal error condition. The initiator may not retry, and typically treats it as a bus error. Note that a target may not deassert DEVSEL# while waiting with TRDY# or STOP# low; it must do this at the beginning of a data phase.


There will always be at least one more cycle after a target-initiated disconnection, to allow the master to deassert FRAME#. There are two sub-cases, which take the same amount of time, but one requires an additional data phase:
Disconnect-A
If the initiator observes STOP# before asserting its own IRDY#, then it can end the burst by deasserting FRAME# at the end of the current data phase.

Disconnect-B
If the initiator has already asserted IRDY# (without deasserting FRAME#) by the time it observes the target's STOP#, it is already committed to an additional data phase. The target must wait through an additional data phase, holding STOP# asserted without TRDY#, before the transaction can end.


If the initiator ends the burst at the same time as the target requests disconnection, there is no additional bus cycle.

Burst addressing


For memory space accesses, the words in a burst may be accessed in several orders. The unnecessary low-order address bits AD[1:0] are used to convey the initiator's requested order. A target which does not support a particular order must terminate the burst after the first word. Some of these orders depend on the cache line size, which is configurable on all PCI devices.
PCI burst ordering
A[1] A[0] Burst order (with 16-byte cache line)
0 0 Linear incrementing (0x0C, 0x10, 0x14, 0x18, 0x1C, ...)
0 1 Cacheline toggle (0x0C, 0x08, 0x04, 0x00, 0x1C, 0x18, ...)
1 0 Cacheline wrap (0x0C, 0x00, 0x04, 0x08, 0x1C, 0x10, ...)
1 1 Reserved (disconnect after first transfer)


If the starting offset within the cache line is zero, all of these modes reduce to the same order.

Cache line toggle and cache line wrap modes are two forms of critical-word-first cache line fetching. Toggle mode XORs the supplied address with an incrementing counter. This is the native order for Intel 486 and Pentium processors. It has the advantage that it is not necessary to know the cache line size to implement it.

PCI version 2.1 obsoleted toggle mode and added the cache line wrap mode,http://download.intel.com/design/chipsets/applnots/27301101.pdf where fetching proceeds linearly, wrapping around at the end of each cache line. When one cache line is completely fetched, fetching jumps to the starting offset in the next cache line.

Note that most PCI devices only support a limited range of typical cache line sizes; if the cache line size is programmed to an unexpected value, they force single-word access.

PCI also supports burst access to I/O and configuration space, but only linear mode is supported. (This is rarely used, and may be buggy in some devices; they may not support it, but not properly force single-word access either.)

Transaction examples


This is the highest-possible speed four-word write burst, terminated by the master:


0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
___ ___ ___ ___ ___
AD[31:0] ---<___X___X___X___X___>---<___>
___ ___ ___ ___ ___
C/BE[3:0]# ---<___X___X___X___X___>---<___>
| | | | ___
IRDY# ^^^^^^^^\______________/ ^^^^^
| | | | ___
TRDY# ^^^^^^^^\______________/ ^^^^^
| | | | ___
DEVSEL# ^^^^^^^^\______________/ ^^^^^
___ | | | ___
FRAME# \_______________/ | ^^^^\____
_ _ |_ |_ |_ |_ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
0 1 2 3 4 5 6 7

On clock edge 1, the initiator starts a transaction by driving an address, command, and asserting FRAME# The other signals are idle (indicated by ^^^), pulled high by the motherboard's pull-up resistors. That might be their turnaround cycle. On cycle 2, the target asserts both DEVSEL# and TRDY#. As the initiator is also ready, a data transfer occurs. This repeats for three more cycles, but before the last one (clock edge 5), the master deasserts FRAME#, indicating that this is the end. On clock edge 6, the AD bus and FRAME# are undriven (turnaround cycle) and the other control lines are driven high for 1 cycle. On clock edge 7, another initiator can start a different transaction. This is also the turnaround cycle for the other control lines.

The equivalent read burst takes one more cycle, because the target must wait 1 cycle for the AD bus to turn around before it may assert TRDY#:

0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
___ ___ ___ ___ ___
AD[31:0] ---<___>---<___X___X___X___>---<___>
___ _______ ___ ___ ___
C/BE[3:0]# ---<___X_______X___X___X___>---<___>
___ | | | | ___
IRDY# ^^^^\___________________/ ^^^^^
___ _____ | | | | ___
TRDY# ^^^^ \______________/ ^^^^^
___ | | | | ___
DEVSEL# ^^^^\___________________/ ^^^^^
___ | | | ___
FRAME# \___________________/ | ^^^^\____
_ _ _ |_ |_ |_ |_ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
0 1 2 3 4 5 6 7 8


A high-speed burst terminated by the target will have an extra cycle at the end:

0_ 1_ 2_ 3_ 4_ 5_ 6_ 7_ 8_
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
___ ___ ___ ___ ___
AD[31:0] ---<___>---<___X___X___X___XXXX>----
___ _______ ___ ___ ___ ___
C/BE[3:0]# ---<___X_______X___X___X___X___>----
| | | | ___
IRDY# ^^^^^^^\_______________________/
_____ | | | | _______
TRDY# ^^^^^^^ \______________/
________________ | ___
STOP# ^^^^^^^ | | | \_______/
| | | | ___
DEVSEL# ^^^^^^^\_______________________/
___ | | | | ___
FRAME# \_______________________/ ^^^^
_ _ _ |_ |_ |_ |_ _ _
CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \
0 1 2 3 4 5 6 7 8

On clock edge 6, the target indicates that it wants to stop (with data), but the initiator is already holding IRDY# low, so there is a fifth data phase (clock edge 7), during which no data is transferred.

Parity


The PCI bus detects parity errors, but does not attempt to correct them by retrying operations; it is purely a failure indication. Because of this, there is no need to detect the parity error before it has happened, and the PCI bus actually detects it a few cycles later. During a data phase, whichever device is driving the AD[31:0] lines computes even parity over them and the C/BE[3:0]# lines, and sends that out the PAR line one cycle later. All access rules and turnaround cycles for the AD bus apply to the PAR line, just one cycle later. The device listening on the AD bus checks the received parity and asserts the PERR# (parity error) line one cycle after that. This generally generates a processor interrupt, and the processor can search the PCI bus for the device which detected the error.

The PERR# line is only used during data phases, once a target has been selected. If a parity error is detected during an address phase (or the data phase of a Special Cycle), the devices which observe it assert the SERR# (System error) line.

Even when some bytes are masked by the C/BE# lines and not in use, they must still have some defined value, and this value must be used to compute the parity.

Fast back-to-back transactions


Due to the need for a turnaround cycle between different devices driving PCI bus signals, in general it is necessary to have an idle cycle between PCI bus transactions. However, in some circumstances it is permitted to skip this idle cycle, going directly from the final cycle of one transfer (IRDY# asserted, FRAME# deasserted) to the first cycle of the next (FRAME# asserted, IRDY# deasserted).

An initiator may only perform back-to-back transactions when:
  • they are by the same initiator (or there would be no time to turn around the C/BE# and FRAME# lines),
  • the first transaction was a write (so there is no need to turn around the AD bus), and
  • the initiator still has permission (from its GNT# input) to use the PCI bus.


Additional timing constraints may come from the need to turn around are the target control lines, particularly DEVSEL#. The target deasserts DEVSEL#, driving it high, in the cycle following the final data phase, which in the case of back-to-back transactions is the first cycle of the address phase. The second cycle of the address phase is then reserved for DEVSEL# turnaround, so if the target is different from the previous one, it must not assert DEVSEL# until the third cycle (medium DEVSEL speed).

One case where this problem cannot arise is if the initiator knows somehow (presumably because the addresses share sufficient high-order bits) that the second transfer is addressed to the same target as the previous one. In that case, it may perform back-to-back transactions. All PCI targets must support this.

It is also possible for the target keeps track of the requirements. If it never does fast DEVSEL, they are met trivially. If it does, it must wait until medium DEVSEL time unless:
  • the current transaction was preceded by an idle cycle (is not back-to-back), or
  • the previous transaction was to the same target, or
  • the current transaction began with a double address cycle.


Targets which have this capability indicate it by a special bit in a PCI configuration register, and if all targets on a bus have it, all initiators may use back-to-back transfers freely.

A subtractive decoding bus bridge must know to expect this extra delay in the event of back-to-back cycles in order to advertise back-to-back support.

64-bit PCI



The PCI specification includes optional 64-bit support. This is provided via an extended connector which provides the 64-bit bus extensions AD[63:32], C/BE[7:4]#, and PAR64, and a number of additional power and ground pins. The 64-bit PCI connector can be distinguished from 32-bit by being longer, and from PCI-X by having three segments, with the one in the middle much shorter than the others. PCI-X slots can be distinguished from 64-bit PCI as the small segment is first, instead of in the center. 32-bit PCI cards will function properly in a PCI-X slot, but PCI-X cards do not work in a standard 32 bit PCI slot..

Memory transactions between 64-bit devices may use all 64 bits to double the data transfer rate. Non-memory transactions (including configuration and I/O space accesses) may not use the 64-bit extension. During a 64-bit burst, burst addressing works just as in a 32-bit transfer, but the address is incremented twice per data phase. The starting address must be 64-bit aligned; i.e. AD2 must be 0. The data corresponding to the intervening addresses (with AD2 = 1) is carried on the upper half of the AD bus.

To initiate a 64-bit transaction, the initiator drives the starting address on the AD bus and asserts REQ64# at the same time as FRAME#. If the selected target can support a 64-bit transfer for this transaction, it replies by asserting ACK64# at the same time as DEVSEL#. Note that a target may decide on a per-transaction basis whether to allow a 64-bit transfer.

If REQ64# is asserted during the address phase, the initiator also drives the high 32 bits of the address and a copy of the bus command on the high half of the bus. If the address requires 64 bits, a dual address cycle is still required, but the high half of the bus carries the upper half of the address and the final command code during both address phase cycles; this allows a 64-bit target to see the entire address and begin responding earlier.

If the initiator sees DEVSEL# asserted without ACK64#, it performs 32-bit data phases. The data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase. Typically, the initiator drives all 64 bits of data before seeing DEVSEL#. If ACK64# is missing, it may cease driving the upper half of the data bus.

The REQ64# and ACK64# lines are held asserted for the entire transaction save the last data phase, and deasserted at the same time as FRAME# and DEVSEL#, respectively.

The PAR64 line operates just like the PAR line, but provides even parity over AD[63:32] and C/BE[7:4]#. It is only valid for address phases if REQ64# is asserted. PAR64 is only valid for data phases if both REQ64# and ACK64# are asserted.

Some 64-bit PCI cards will work in 32-bit mode if inserted in shorter 32-bit connectors, with half the edge connections not connected and overhanging, so long as there are no motherboard components positioned so as to mechanically obstruct the overhanging card. An example is the Adaptec 29160 64-bit SCSI
SCSI
Small Computer System Interface is a set of standards for physically connecting and transferring data between computers and peripheral devices. The SCSI standards define commands, protocols, and electrical and optical interfaces. SCSI is most commonly used for hard disks and tape drives, but it...

 interface card.

Cache snooping (obsolete)


PCI originally included optional support for write-back cache coherence
Cache coherence
In computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...

. This required support by cacheable memory targets, which would listen to two pins from the cache on the bus, SDONE (snoop done) and SBO# (snoop backoff).

Because this was rarely implemented in practice, it was deleted from revision 2.2 of the PCI specification, and the pins re-used for SMBus access in revision 2.3.

The cache would watch all memory accesses, without asserting DEVSEL#. If it noticed an access that might be cached, it would drive SDONE low (snoop not done). A coherence-supporting target would avoid completing a data phase (asserting TRDY#) until it observed SDONE high.

In the case of a write to data that was clean in the cache, the cache would only have to invalidate its copy, and would assert SDONE as soon as this was established. However, if the cache contained dirty data, the cache would have to write it back before the access could proceed. so it would assert SBO# when raising SDONE. This would signal the active target to assert STOP# rather than TRDY#, causing the initiator to disconnect and retry the operation later. In the meantime, the cache would arbitrate for the bus and write its data back to memory.

Targets supporting cache coherency are also required to terminate bursts before they cross cache lines.

Development tools



When developing and/or troubleshooting the PCI bus, examination of hardware signals can be very important. Logic analyzers and bus analyzer
Bus analyzer
A bus analyzer is a computer bus analysis tool, often a combination of hardware and software, used during development of hardware or device drivers for a specific bus, for diagnosing bus or device failures, or reverse engineering....

s are tools which collect, analyze, decode signals for users to view in useful ways.

Further reading


Official Technical Specifications ($1000 for non-members or $50 for members. PCI-SIG membership is $3000 per year.) ($1000 for non-members or $50 for members. PCI-SIG membership is $3000 per year.)
Books
  • PCI Bus Demystified; 2nd Ed; Doug Abbott; 250 pages; 2004; ISBN 9780750677394.
  • PCI System Architecture; 4th Ed; Tom Shanley; 832 pages; 1999; ISBN 9780201309744.
  • PCI-X System Architecture; 1st Ed; Tom Shanley; 752 pages; 2000; ISBN 9780201726824.
  • PCI & PCI-X Hardware and Software Architecture & Design; 5th Ed; Ed Solari; 1140 pages; 2001; ISBN 9780929392639.
  • PCI HotPlug Application and Design; 1st Ed; Alan Goodrum; 162 pages; 1998; ISBN 9780929392608.


External links



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