OpenSPARC
Encyclopedia
OpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems
' register-transfer level (RTL) Verilog
code for a full 64-bit
, 32-thread microprocessor
, the UltraSPARC T1
processor. On 21 March 2006, Sun released the source code to the T1 IP core under the GNU General Public License
. The full OpenSPARC T1 system consists of 8 cores, each one capable to execute 4 threads concurrently, for a total of 32 threads. Each core executes instruction in order and its logic is split among 6 pipeline stages.
On December 11, 2007, Sun also made the UltraSPARC T2
processor's RTL available via the OpenSPARC project. OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.
Sun Microsystems
Sun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...
' register-transfer level (RTL) Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
code for a full 64-bit
64-bit
64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...
, 32-thread microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
, the UltraSPARC T1
UltraSPARC T1
|right|262px|UltraSPARC T1 processorSun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU...
processor. On 21 March 2006, Sun released the source code to the T1 IP core under the GNU General Public License
GNU General Public License
The GNU General Public License is the most widely used free software license, originally written by Richard Stallman for the GNU Project....
. The full OpenSPARC T1 system consists of 8 cores, each one capable to execute 4 threads concurrently, for a total of 32 threads. Each core executes instruction in order and its logic is split among 6 pipeline stages.
On December 11, 2007, Sun also made the UltraSPARC T2
UltraSPARC T2
Sun Microsystems' UltraSPARC T2 microprocessor is a multithreading, multi-core CPU. It is a member of the SPARC family, and the successor to the UltraSPARC T1. The chip is sometimes referred to by its codename, Niagara 2...
processor's RTL available via the OpenSPARC project. OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.
See also
- LEONLEONLEON is a 32-bit CPU microprocessor core, based on the SPARC-V8 RISC architecture and instruction set. It was originally designed by the European Space Research and Technology Centre , part of the European Space Agency , and after that by Gaisler Research. It is described in synthesizable VHDL...
- OpenRISCOpenRISCOpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures...
- S1 CoreS1 CoreS1 Core is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the OpenSPARC project.The main goal of the project is to keep the S1 Core as...
(a derived single-core implementation) - SPARCSPARCSPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....
(Scalable Processor ARChitecture) - Field-programmable gate arrayField-programmable gate arrayA field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...