LEON
Encyclopedia
LEON is a 32-bit
CPU
microprocessor
core, based on the SPARC
-V8 RISC architecture and instruction set
. It was originally designed by the European Space Research and Technology Centre
(ESTEC), part of the European Space Agency
(ESA), and after that by Gaisler Research. It is described in synthesizable VHDL
. LEON has a dual license model: A LGPL
/GPL
FLOSS
license that can be used without licensing fee, or a proprietary license that can be purchased for integration in a proprietary product.
The core is configurable through VHDL generics, and is used in system-on-a-chip (SOC)
designs both in research and commercial settings.
The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost. Another objective was to be able to manufacture in a Single Event Upset (SEU) sensitive semiconductor process. To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed. The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient (SET) errors in combinational logic.
The LEON family includes the first LEON1 VHSIC Hardware Description Language (VHDL) design that was used in the LEONExpress test chip developed in 0.25 μm technology to prove the fault-tolerance concept. The second LEON2 VHDL design was used in the processor device AT697 from Atmel (F) and various system-on-chip devices. These two LEON implementations were developed by ESA. Gaisler Research, now Aeroflex Gaisler, developed the third LEON3 design and has announced the availability of the fourth generation LEON, the LEON4 processor.
such as an FPGA
or manufactured into an ASIC
. This section and the subsequent subsections focus on the LEON processors as soft IP cores and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution.
All processors in the LEON series are based on the SPARC
-V8 RISC
architecture. LEON2(-FT) has a five-stage pipeline while later versions have a seven-stage pipeline. LEON2 and LEON2-FT are distributed as a system-on-chip design that can be modified using a graphical configuration tool. While the LEON2(-FT) design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design.
The standard LEON2(-FT) distribution includes the following support cores:
The LEON3, LEON3FT and LEON4 cores are typically used together with the GRLIB IP Library. While the LEON2 distributions contain one design that can be used on several target technologies, GRLIB contains several template designs, both for FPGA development boards and for ASIC
targets that can be modified using a graphical configuration tool similar to the one in the LEON2 distribution. The LEON/GRLIB package contains a larger number of cores compared to the LEON2 distributions and also include a plug and play extension to the on-chip AMBA
bus. IP cores available in GRLIB include:
tolerant version of the LEON2 processor. Flip-flops are protected by triple modular redundancy
and all internal and external memories are protected by EDAC or parity bit
s. Special licence restrictions apply to this IP (distributed by the European Space Agency
).
There are several differences between the two LEON2 processor models and the LEON3. LEON3 includes SMP
support and a seven-stage pipeline, while LEON2 does not support SMP and has a five-stage pipeline.
The following features of the standard LEON3 processor are not supported by LEON3FT
The LEON3FT core is distributed together with a special FT version of the GRLIP IP library. Only netlist distribution is possible.
A FPGA implementation called LEON3FT-RTAX is proposed for critical space applications.
-V8 architecture of the LEON core is not well-supported among Real-time operating system
s as can be seen in the list of real-time operating systems. The Real-time operating system
s that support the LEON core, are currently RTLinux
, PikeOS
, eCos
, RTEMS
, Nucleus, ThreadX, VxWorks
(as per a port by Gaisler Research), LynxOS
(also per a port by Gaisler Research) and POK (a free ARINC653 implementation released under the BSD licence).
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
CPU
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
core, based on the SPARC
SPARC
SPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....
-V8 RISC architecture and instruction set
Instruction set
An instruction set, or instruction set architecture , is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O...
. It was originally designed by the European Space Research and Technology Centre
European Space Research and Technology Centre
The European Space Research and Technology Centre is the European Space Agency's main technology development and test centre for spacecraft and space technology. It is situated in Noordwijk, South Holland, in the western Netherlands....
(ESTEC), part of the European Space Agency
European Space Agency
The European Space Agency , established in 1975, is an intergovernmental organisation dedicated to the exploration of space, currently with 18 member states...
(ESA), and after that by Gaisler Research. It is described in synthesizable VHDL
VHSIC Hardware Description Language
VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.- History :...
. LEON has a dual license model: A LGPL
GNU Lesser General Public License
The GNU Lesser General Public License or LGPL is a free software license published by the Free Software Foundation . It was designed as a compromise between the strong-copyleft GNU General Public License or GPL and permissive licenses such as the BSD licenses and the MIT License...
/GPL
GNU General Public License
The GNU General Public License is the most widely used free software license, originally written by Richard Stallman for the GNU Project....
FLOSS
Floss
Floss may refer to:* Dental floss, used to clean teeth* Embroidery thread, machine or hand-spun yarn for embroidery* Fairy floss or candyfloss, alternative names for cotton candy* Rousong, i.e. meat floss-Computing:...
license that can be used without licensing fee, or a proprietary license that can be purchased for integration in a proprietary product.
The core is configurable through VHDL generics, and is used in system-on-a-chip (SOC)
System-on-a-chip
A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
designs both in research and commercial settings.
History
The LEON project was started by the European Space Agency (ESA) in late 1997 to study and develop a high-performance processor to be used in European space projects.The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost. Another objective was to be able to manufacture in a Single Event Upset (SEU) sensitive semiconductor process. To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed. The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient (SET) errors in combinational logic.
The LEON family includes the first LEON1 VHSIC Hardware Description Language (VHDL) design that was used in the LEONExpress test chip developed in 0.25 μm technology to prove the fault-tolerance concept. The second LEON2 VHDL design was used in the processor device AT697 from Atmel (F) and various system-on-chip devices. These two LEON implementations were developed by ESA. Gaisler Research, now Aeroflex Gaisler, developed the third LEON3 design and has announced the availability of the fourth generation LEON, the LEON4 processor.
LEON processor models and distributions
A LEON processor can be implemented in programmable logicProgrammable logic device
A programmable logic device or PLD is an electronic component used to build reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture...
such as an FPGA
Field-programmable gate array
A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...
or manufactured into an ASIC
Application-specific integrated circuit
An application-specific integrated circuit is an integrated circuit customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC...
. This section and the subsequent subsections focus on the LEON processors as soft IP cores and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution.
All processors in the LEON series are based on the SPARC
SPARC
SPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....
-V8 RISC
Reduced instruction set computer
Reduced instruction set computing, or RISC , is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer...
architecture. LEON2(-FT) has a five-stage pipeline while later versions have a seven-stage pipeline. LEON2 and LEON2-FT are distributed as a system-on-chip design that can be modified using a graphical configuration tool. While the LEON2(-FT) design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design.
The standard LEON2(-FT) distribution includes the following support cores:
- Interrupt controller
- Debug support unit with trace buffer
- Two 24-bit timers
- Two UARTs
- 16-bit I/O port
- Memory controller.
The LEON3, LEON3FT and LEON4 cores are typically used together with the GRLIB IP Library. While the LEON2 distributions contain one design that can be used on several target technologies, GRLIB contains several template designs, both for FPGA development boards and for ASIC
ASIC
ASIC may refer to:* Application-specific integrated circuit, an integrated circuit developed for a particular use, as opposed to a customised general-purpose device.* ASIC programming language, a dialect of BASIC...
targets that can be modified using a graphical configuration tool similar to the one in the LEON2 distribution. The LEON/GRLIB package contains a larger number of cores compared to the LEON2 distributions and also include a plug and play extension to the on-chip AMBA
Advanced Microcontroller Bus Architecture
The Advanced Microcontroller Bus Architecture is used as the on-chip bus in system-on-a-chip designs. Since its inception, the scope of AMBA has gone far beyond microcontroller devices, and is now widely used on a range of ASIC and SoC parts including applications processors used in modern...
bus. IP cores available in GRLIB include:
- 32-bit SDRAM controller
- 32-bit PCI bridge with DMADirect memory accessDirect memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....
- 10/100/1000 Mbit EthernetEthernetEthernet is a family of computer networking technologies for local area networks commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely replaced competing wired LAN technologies....
MAC - 8/16/32-bit PROMProgrammable read-only memoryA programmable read-only memory or field programmable read-only memory or one-time programmable non-volatile memory is a form of digital memory where the setting of each bit is locked by a fuse or antifuse. Such PROMs are used to store programs permanently...
and SRAM controller - 16/32/64-bit DDR/DDR2 controllers
- USBUniversal Serial BusUSB is an industry standard developed in the mid-1990s that defines the cables, connectors and protocols used in a bus for connection, communication and power supply between computers and electronic devices....
2.0 host and device controllers - CANController Area NetworkController–area network is a vehicle bus standard designed to allow microcontrollers and devices to communicate with each other within a vehicle without a host computer....
controller - TAP controller
- SPI, I2C, ATA controllers
- UART with FIFO
- Modular timer unit
- Interrupt controller
- General purpose I/O port
FPGA Design Flow
Design Flow Documentation for the LEON into FPGA are available from the manufacturer and from third party resources.Terminology
The term LEON2/LEON2-FT often refer to the LEON2 system-on-chip design, which is the LEON2 processor core together with the standard set of peripherals available in the LEON2(-FT) distribution. Later processors in the LEON series are used in a wide range of designs and are therefore not as tightly coupled with a standard set of peripherals. With LEON3 and LEON4 the name typically refers to only the processor core, while LEON/GRLIB is used to refer to the complete system-on-chip design.LEON2 processor core
LEON2 has the following characteristics:- The GNU LGPLGNU Lesser General Public LicenseThe GNU Lesser General Public License or LGPL is a free software license published by the Free Software Foundation . It was designed as a compromise between the strong-copyleft GNU General Public License or GPL and permissive licenses such as the BSD licenses and the MIT License...
allows a high degree of freedom of intervention on the freely-available source code. - Configurability is a key feature of the project, and is achieved through the usage of VHDL generics.
- It offers all basic functions of a pipelined in-order processor.
- It is a fairly-sized VHDL project (about 90 files, for the complete LEON2 distribution, including peripheral IP cores)
LEON2-FT processor core
The LEON2-FT processor is the single event upsetSingle event upset
A single event upset is a change of state caused by ions or electro-magnetic radiation striking a sensitive node in a micro-electronic device, such as in a microprocessor, semiconductor memory, or power transistors. The state change is a result of the free charge created by ionization in or close...
tolerant version of the LEON2 processor. Flip-flops are protected by triple modular redundancy
Triple modular redundancy
In computing, triple modular redundancy is a fault tolerant form of N-modular redundancy, in which three systems perform a process and that result is processed by a voting system to produce a single output. If any one of the three systems fails, the other two systems can correct and mask the...
and all internal and external memories are protected by EDAC or parity bit
Parity bit
A parity bit is a bit that is added to ensure that the number of bits with the value one in a set of bits is even or odd. Parity bits are used as the simplest form of error detecting code....
s. Special licence restrictions apply to this IP (distributed by the European Space Agency
European Space Agency
The European Space Agency , established in 1975, is an intergovernmental organisation dedicated to the exploration of space, currently with 18 member states...
).
LEON3 processor core
The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing use for any purpose without licensing fee. LEON3 is also available under a proprietary license, allowing it to be used in proprietary applications.There are several differences between the two LEON2 processor models and the LEON3. LEON3 includes SMP
Symmetric multiprocessing
In computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...
support and a seven-stage pipeline, while LEON2 does not support SMP and has a five-stage pipeline.
LEON3-FT processor core
The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct single event upset (SEU) errors in all on-chip RAM memories. The LEON3FT processor support most of the functionality in the standard LEON3 processor, and adds the following features:- Register fileRegister fileA register file is an array of processor registers in a central processing unit . Modern integrated circuit-based register files are usually implemented by way of fast static RAMs with multiple ports...
SEU error-correction of up to 4 errors per 32-bit word - Cache memory error-correction of up to 4 errors per tag or 32-bit word
- Autonomous and software transparent error handling
- No timing impact due to error detection or correction
The following features of the standard LEON3 processor are not supported by LEON3FT
- Local scratchpad RAMScratchpad RAMScratchpad memory , also known as scratchpad, scatchpad RAM or local store in computer terminology, is a high-speed internal memory used for temporary storage of calculations, data, and other work in progress...
(neither for instruction nor for data) - Cache locking
- LRR (least recently replaced) cache replacement algorithmCache algorithmsIn computing, cache algorithms are optimizing instructions – algorithms – that a computer program or a hardware-maintained structure can follow to manage a cache of information stored on the computer...
The LEON3FT core is distributed together with a special FT version of the GRLIP IP library. Only netlist distribution is possible.
A FPGA implementation called LEON3FT-RTAX is proposed for critical space applications.
LEON4 processor core
In January 2010, the fourth version of the LEON processor was released. This release has the following new features:- Static branch prediction added to pipeline
- Optional level-2 cache
- 64-bit or 128-bit path to AMBA AHB interface
- Higher performance possible (claimed by manufacturer: 1.7 DMIPS/MHz as opposed to 1.4 DMIPS/MHz of LEON3)
Real-time OS support
The SPARCSPARC
SPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....
-V8 architecture of the LEON core is not well-supported among Real-time operating system
Real-time operating system
A real-time operating system is an operating system intended to serve real-time application requests.A key characteristic of a RTOS is the level of its consistency concerning the amount of time it takes to accept and complete an application's task; the variability is jitter...
s as can be seen in the list of real-time operating systems. The Real-time operating system
Real-time operating system
A real-time operating system is an operating system intended to serve real-time application requests.A key characteristic of a RTOS is the level of its consistency concerning the amount of time it takes to accept and complete an application's task; the variability is jitter...
s that support the LEON core, are currently RTLinux
RTLinux
RTLinux or RTCore is a hard realtime RTOS microkernel that runs the entire Linux operating system as a fully preemptive process.It was developed by Victor Yodaiken , Michael Barabanov , Cort Dougan and others at the New Mexico Institute of Mining and Technology and then as a commercial product at...
, PikeOS
PikeOS
PikeOS is a microkernel-based real-time operating system made by SYSGO AG. It is targeted at safety and security critical embedded systems. It provides a partitioned environment for multiple operating systems with different design goals, safety requirements, or security requirements to coexist in a...
, eCos
ECos
eCos is an open source, royalty-free, real-time operating system intended for embedded systems and applications which need only one process with multiple threads. It is designed to be customizable to precise application requirements of run-time performance and hardware needs...
, RTEMS
RTEMS
RTEMS is a free open source real-time operating system designed for embedded systems....
, Nucleus, ThreadX, VxWorks
VxWorks
VxWorks is a real-time operating system developed as proprietary software by Wind River Systems of Alameda, California, USA. First released in 1987, VxWorks is designed for use in embedded systems.- History :...
(as per a port by Gaisler Research), LynxOS
LynxOS
The LynxOS RTOS is a Unix-like real-time operating system from LynuxWorks . Sometimes known as the Lynx Operating System, LynxOS features full POSIX conformance and, more recently, Linux compatibility...
(also per a port by Gaisler Research) and POK (a free ARINC653 implementation released under the BSD licence).
See also
- OpenSPARCOpenSPARCOpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level Verilog code for a full 64-bit, 32-thread microprocessor, the UltraSPARC T1 processor. On 21 March 2006, Sun released the source code to the...
- S1 CoreS1 CoreS1 Core is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the OpenSPARC project.The main goal of the project is to keep the S1 Core as...
- OpenRISCOpenRISCOpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures...
- ERC32ERC32ERC32 is a radiation-tolerant 32-bit RISC processor developed for space applications. It was developed by Temic . Two versions have been manufactured, the ERC32 Chip Set , and the ERC32 Single Chip . These implementations follows SPARC V7 specifications...
- Soft microprocessorSoft microprocessorA soft microprocessor is a microprocessor core that can be wholly implemented using logic synthesis...