SPARC

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SPARC

SPARC (from Scalable Processor Architecture) is a RISCReduced instruction set computer Overview

The reduced instruction set computer, or RISC, is a microprocessor CPU design philosophy that favors a simpler set of ...
microprocessorMicroprocessor

A microprocessor is a digital electronic component with transistors on a single semiconductor integrated circuit ....
instruction setInstruction set Summary

An instruction set, or instruction set architecture , is the part of the computer architecture related to programming,...
architectureComputer architecture

In computer engineering, computer architecture is the conceptual design and fundamental operational structure of a computer ...
originally designed in 1985 by Sun MicrosystemsSun Microsystems Summary

company_name = Sun Microsystems | company_type = Public |...
.

SPARC is a registered trademark of SPARC International, Inc.Incorporation (business)

Incorporation is the forming of a new corporation....
, an organization established in 1989 to promote the SPARC architecture and to provide conformance testingConformance testing

Conformance testing or type testing is testing to determine whether a system meets some specified standard....
. SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas InstrumentsTexas Instruments

| homepage =}}Texas Instruments , better known in the electronics industry as TI, is an American company ba...
, AtmelAtmel

Atmel Corporation is a manufacturer of semiconductors, founded in 1984 by George Perlegos....
, Cypress SemiconductorCypress Semiconductor

Cypress Semiconductor is a semiconductor design and manufacturing company....
, and FujitsuFujitsu

is a Japanese company specializing in semiconductors, computers , telecommunications, and services, and is headquartered in Tokyo....
. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.

Implementations of the SPARC architecture were initially designed and used for Sun's Sun-4Sun-4

Sun-4 was the name given to a series of UNIX computer workstations and servers produced by Sun Microsystems, launched in 198...
workstation and serverServer (computing)

In information technology, a server is a computer system that provides services to other computing systems—called clie...
systems, replacing their earlier Sun-3Sun-3

Sun-3 was the name given to a series of UNIX computer workstations and servers produced by Sun Microsystems, launched in 198...
systems based on the Motorola 68000 family of processors. Later, SPARC processors were used in SMPSymmetric multiprocessing

Symmetric Multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors ar...
servers produced by Sun MicrosystemsSun Microsystems

company_name = Sun Microsystems | company_type = Public |...
, Solbourne and FujitsuFujitsu Summary

is a Japanese company specializing in semiconductors, computers , telecommunications, and services, and is headquartered in Tokyo....
, among others.

Features

The SPARC architecture was heavily influenced by the earlier RISC designs including the RISCBerkeley RISC

Berkeley RISC was one of two seminal research projects into RISC-based microprocessor design taking place under ARPA's VLSI ...
I & II from the University of California, BerkeleyUniversity of California, Berkeley

The University of California, Berkeley is the oldest and flagship campus of the ten-campus University of California system....
and the IBM 801IBM 801

The 801 was a RISC microprocessor architecture designed by IBM in the 1970s, and used in various roles in IBM until the 1980...
. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycleClock signal

In electronics and especially synchronous digital circuits, a clock signal is a signal used to coordinate the actions of two...
. This made them similar to the MIPS architectureFacts About MIPS architecture

MIPS, for Microprocessor without interlocked pipeline stages, is a RISC microprocessor architecture d...
in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slotBranch delay slot

In computer architecture, a branch delay instruction is an instruction immediately following a conditional branch instructio...
.

The SPARC processor usually contains as many as 128 general purpose registersProcessor register

In computer architecture, a processor register is a small amount of very fast computer memory used to speed the execution of...
.
At any point, only 32 of them are immediately visible to software - 8 are global registers (one of which, g0, is hard-wireHard-wire

Hardwire may be a reference to:*Hardwired, the default definition;...
d to zero, so only 7 of them are usable as registers) and the other 24 are from the stackStack (data structure)

In computer science, a stack is a temporary abstract data type and data structure based on the principle of Last In First ...
of registers. These 24 registers form what is called a register windowRegister window

In computer engineering, the use of register windows is a technique to improve the performance of a particularly common oper...
, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.
The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (nonprivileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from 3 to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stackCall stack

In computer science, a call stack is a special stack which stores information about the active subroutines of a computer pro...
efficiency, or to implement only 3 to reduce context switching time, or to implement some number between them. Other architectures that include similar register fileRegister file

A register file is an array of processor registers in a central processing unit....
features include Intel i960Intel i960

Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontrolle...
, IA-64IA-64

In computing, IA-64 is a 64-bit processor architecture developed cooperatively by Intel Corporation and Hewlett-Packard, and...
, and AMD 29000.

The architecture has gone through a few revisions. It gained hardware multiply and divide functionality in Version 8. The most substantial upgrade resulted in Version 9, which is a 64-bit64-bit

As of 2004, 64-bit CPUs are common in servers, and have recently been introduced to the mainstream personal computer arena i...
(addressing and data) SPARC specification.

In SPARC Version 8, the floating pointFloating point

Floating-point is a means of representing real numbers in terms of digits or bits in a computer or calculator, similar to ho...
register file has 16 double precisionDouble precision Summary

In computing, double precision is a computer numbering format that occupies two storage locations in computer memory at addr...
registers.
Each of them can be used as two single precisionSingle precision

In computing, single precision is a computer numbering format that occupies one storage location in computer memory at a giv...
registers, providing a total of 32 single precision registers.
An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers.
SPARC Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers.

Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run timeRun-time system Summary

In computer science, the runtime system is software that provides services for a running program but is itself not considere...
for MLML programming language

ML is a general-purpose functional programming language developed by Robin Milner and others in the late 1970s at the Univer...
, LispLisp programming language

Lisp is a family of computer programming languages with a long history and a distinctive fully-parenthesized syntax....
, and similar languages that might use a tagged integer format.

The 32-bit32-bit

32-bit is also a term given to a generation of computers in which 32-bit processors were the norm....
SPARC V8 architecture is purely big-endianEndianness

In computing, endianness generally refers to sequencing methods used in a one-dimensional system ....
. The 64-bit SPARC V9 architecture utilizes big-endianEndianness

In computing, endianness generally refers to sequencing methods used in a one-dimensional system ....
instructions, but can access data in either big-endianEndianness

In computing, endianness generally refers to sequencing methods used in a one-dimensional system ....
or little-endianEndianness

In computing, endianness generally refers to sequencing methods used in a one-dimensional system ....
byte order, chosen either at the application instruction (load/store) level or at the memory pagePaging

In computer operating systems, paging memory allocation algorithms divide computer memory into small partitions, and allocat...
level (via an MMU setting). The latter is often used for accessing data from inherently little-endianEndianness

In computing, endianness generally refers to sequencing methods used in a one-dimensional system ....
devices, such as those on PCI buses.

History

There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. SPARC V8 was standardized as IEEE 1754-1994, an IEEE standard for a 32-bit microprocessor architecture. SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. UltraSPARC Architecture 2005 includes not only the nonprivileged and most of the privileged portions of SPARC V9, but also all the architectural extensions (such as CMT, hyperprivileged, VISVisual Instruction Set

Visual Instruction Set is a SIMD instruction set used on the SPARC series of CPUs, implemented only on the 64-bit UltraS...
1, and VIS 2) present in Sun's UltraSPARC processors starting with the UltraSPARC T1UltraSPARC T1

Sun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "'...
implementation. UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification. The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations.

As of December 2005 Sun announced their UltraSPARC T1 design would be open sourced, and in March 2006 the full source code became available via the OpenSPARCOpenSPARC

OpenSPARC is an open source hardware project started in December 2005....
project.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPECStandard Performance Evaluation Corporation

The Standard Performance Evaluation Corporation is a non-profit organization that aims to produce fair, impartial and meanin...
CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

SPARC64

Since 1995, FujitsuFujitsu

is a Japanese company specializing in semiconductors, computers , telecommunications, and services, and is headquartered in Tokyo....
(initially through its subsidiary, HAL Computer SystemsHAL Computer Systems Overview

HAL Computer Systems was a Campbell, CA-based computer manufacturer....
) has designed SPARC V9-compliant processors under the SPARC64 brand. The latest processors in this series are the
, used in FujitsuFujitsu

is a Japanese company specializing in semiconductors, computers , telecommunications, and services, and is headquartered in Tokyo....
's family of servers; and the SPARC64 VI, used by Sun Microsystems and Fujitsu in their SPARC EnterpriseSPARC Enterprise

The SPARC Enterprise series is a range of UNIX servers co-developed by Sun Microsystems and Fujitsu....
M-class servers.

SPARC microprocessor specifications

Name (Codename)	Model	Frequency [MHz]	Architecture Version	Year	Threads Per Core × Cores = Total Threads	Process [µm]	Transistors [millions]	Die size [mm²]	IO Pins	Power [W]	Voltage [V]	L1 Dcache [k]	L1 Icache [k]	L2 Cache [k]	L3 Cache [k]
SPARC	(various)	14.28–40	V7	1987-1992	1×1=1	0.8–1.3	~0.1–1.8
160–256
0–128 (unified)		none	none
microSPARC I (Tsunami)	TI TMS390S10	40–50	V8	1992	1×1=1	0.8	0.8	225?	288	2.5	5	2	4	none	none
SuperSPARC I (Viking)	TI TMX390Z50 / Sun STP1020	33–60	V8	1992	1×1=1	0.8	3.1
293	14.3	5	16	20	0-2048	none
SPARClite	Fujitsu MB8683x	66–108	V8E	1992	1×1=1
144–176
2.5/3.3V	1–16	1–16	none	none
hyperSPARC (Colorado 1)	Ross RT620A	40–90	V8	1993	1×1=1	0.5	1.5
5?	0	8	128-256	none
microSPARC II (Swift)	Fujitsu MB86904 / Sun STP1012	60–125	V8	1994	1×1=1	0.5	2.3	233	321	5	3.3	8	16	none	none
hyperSPARC (Colorado 2)	Ross RT620B	90–125	V8	1994	1×1=1	0.4	1.5
3.3	0	8	128-256	none
SuperSPARC II (Voyager)	Sun STP1021	75–90	V8	1994	1×1=1	0.8	3.1	299
16
16	20	1024-2048	none
hyperSPARC (Colorado 3)	Ross RT620C	125–166	V8	1995	1×1=1	0.35	1.5
3.3	0	8	512-1024	none
TurboSPARC	Fujitsu MB86907	160–180	V8	1995	1×1=1	0.35	3.0	132	416	7	3.5	16	16	512	none
UltraSPARC I (Spitfire)	Sun STP1030	143–167	V9	1995	1×1=1	0.47	5.2	315	521	30 @167 MHz	3.3	16	16	512-1024	none
UltraSPARC I (Hornet)	Sun STP1030	200	V9	1998	1×1=1	0.42	5.2	265	521
3.3	16	16	512-1024	none
hyperSPARC (Colorado 4)	Ross RT620D	180–200	V8	1996	1×1=1	0.35	1.7
3.3	16	16	512	none
SPARC64	Fujitsu (HAL)	101–118	V9	1995	1×1=1	0.4
297+163+142	286	50	3.8	128	128
SPARC64 II	Fujitsu (HAL)	141–161	V9	1996	1×1=1	0.35
202+103+84	286	64	3.3	128	128
SPARC64 III	Fujitsu (HAL) MBCS70301	250–330	V9	1998	1×1=1	0.24	17.6	240
2.5	64	64	8192
UltraSPARC IIs (Blackbird)	Sun STP1031	250–400	V9	1997	1×1=1	0.35	5.4	149	521	25 @250 MHz	2.5	16	16	1024 or 4096	none
UltraSPARC IIs (Sapphire-Black)	Sun STP1032 / STP1034	360–480	V9	1999	1×1=1	0.25	5.4	126	521	21 @400 MHz	1.9	16	16	1024–8192	none
UltraSPARC IIi (Sabre)	Sun SME1040	270–360	V9	1997	1×1=1	0.35	5.4	156	587	21	1.9	16	16	256–2048	none
UltraSPARC IIi (Sapphire-Red)	Sun SME1430	333–480	V9	1998	1×1=1	0.25	5.4
587	21 @440 MHz	1.9	16	16	2048	none
UltraSPARC IIe (Hummingbird)	Sun SME1701	400–600	V9	2000	1×1=1	0.18 Al
370	13 max @500 MHz	1.5-1.7	16	16	256	none
UltraSPARC IIi (IIe+)	--	550–650	V9	2002	1×1=1	0.18 Cu
370	17.6	1.7	16	16	512	none
SPARC64 GP	Fujitsu SFCB81147	400–810	V9	2000	1×1=1	0.18	30.2	217
1.8	128	128	8192
SPARC64 IV	Fujitsu MBCS80523	450–810	V9	2000	1×1=1	0.13
128	128	2048
UltraSPARC III (Cheetah)	Sun SME1050	600	V9	2001	1×1=1	0.18 Al	29	330	1368	53	1.6	64	32	8192	none
UltraSPARC III (Cheetah)	Sun SME1052	750–900	V9	2001	1×1=1	0.13 Al	29
1368
1.6	64	32	8192	none
UltraSPARC III Cu (Cheetah+)	Sun SME1056	1002–1200	V9	2001	1×1=1	0.13 Cu	29	232	1368	80 @900 MHz	1.6	64	32	8192	none
UltraSPARC IIIi (Jalapeno)	Sun SME1603	1064–1593	V9	2003	1×1=1	0.13	87.5	206	959	52	1.3	64	32	1024	none
SPARC64 V (Zeus)	Fujitsu	1100–1350	V9/JPS1	2003	1×1=1	0.13	190	289	269	40	1.2	128	128	2048
SPARC64 V+ (Olympus-B)	Fujitsu	1650–2160	V9/JPS1	2004	1×1=1	0.09	400	297	279	65	1	128	128	4096
UltraSPARC IV (Jaguar)	Sun SME1167	1050–1350	V9	2004	1×2=2	0.13	66	356	1368	108	1.35	64	32	16384	none
UltraSPARC IV+UltraSPARC IV+ The UltraSPARC IV+ is a microprocessor manufactured by Sun Microsystems.... (Panther)	Sun SME1167A	1500–2100	V9	2005	1×2=2	0.09	295	336	1368	90	1.1	64	64	2048	32768
UltraSPARC T1UltraSPARC T1 Sun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "'... (Niagara)	Sun SME1905	1000–1400	V9 / UA 2005	2005	4×8=32	0.09	300	340	1933	72	1.3	8	16	3072	none
SPARC64 VI (Olympus-C)	Fujitsu	2150–2400	V9/JPS2	2007	2×2=4	0.09	540	422
120
128	128	5120	none
UltraSPARC T2UltraSPARC T2 Sun Microsystems' UltraSPARC T2 microprocessor, is a multithreading, multi-core CPU.... (Niagara 2)	Sun SME1908A	1000–1400	V9 / UA 2007	2007	8×8=64	0.065	503	342	1831	95	1.1–1.5	8	16	4096	none
UltraSPARC T2 Plus (Victoria Falls)	Sun SME1910A	1200–1400	V9 / UA 2007	2008	8×8=64	0.065	503	342	1831	-	-	8	16	4096	none
SPARC64 VII (Jupiter)	Fujitsu	2500	V9/JPS2(?)	2008	2×4=8	0.065	?	?
?
64	64	6144	none
UltraSPARC RK	Sun SME1832	2300	V9 / UA__?__	2009	2×16=32	0.065	?	396	2326	?	?	32	32 + 8 predecoded bits	2048	?
Name	Model	Frequency [MHz]	Architecture Version	Year	Threads Per Core × Cores = Total Threads	Process [µm]	Transistors [millions]	Die size [mm²]	IO Pins	Power [W]	Voltage [V]	L1 Dcache [k]	L1 Icache [k]	L2 Cache [k]	L3 Cache [k]

Operating system support

SPARC machines have generally used Sun's SunOSSunOS

SunOS is a version of the UNIX operating system developed by Sun Microsystems for their workstation and server computer syst...
or Solaris Operating SystemSolaris Operating System

name = Solaris| screenshot = | caption = Solaris 10 using Java Desktop System...
s, but other operating systemOperating system

An operating system is a software program that manages the hardware and software resources of a computer....
s such as NEXTSTEPNEXTSTEP

NEXTSTEP is the original object-oriented, multitasking operating system that NeXT Computer, Inc....
, RTEMSRTEMS

RTEMS is a free open source real-time operating system designed for embedded systems....
, FreeBSDFreeBSD

colspan="2" | FreeBSD|-| colspan="2" style="text-align:center;" | br/>br />FreeBSD welcome screen...
, OpenBSDOpenBSD

! Computer and operating system|-! Unix and Unix-like...
, NetBSDNetBSD

NetBSD is a freely redistributable, open source version of the Unix-like BSD computer operating system....
, and LinuxLinux

Linux is a Unix-like computer operating system....
are also used on SPARC-based systems.

In 1993, IntergraphIntergraph

Intergraph was founded in 1969 as M&S Computing, Inc., by ex-IBM engineers who had been working on the Saturn rocket for the...
announced a port of Windows NTWindows NT

Windows NT is a family of operating systems produced by Microsoft, the first version of which was released in July 1993....
to the SPARC architecture, but it was later canceled.

Open source implementations

Three fully open sourceOpen source

Open source describes practices in production and development that promote access to the end product's sources....
implementations of the SPARC architecture exist.

LEONLeon

Leon or Lon or Len may refer to:...
, a 32-bit, single-thread SPARC Version 8 implementation, designed especially for outer space uses. Source codeSource code

Source code is any series of statements written in some human-readable computer programming language....
is written in VHDLVHSIC Hardware Description Language

VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-...
, and licensed under the GPLGNU General Public License

The GNU General Public License is a widely used free software license, originally written by Richard Stallman for the GNU p...
.
OpenSPARCOpenSPARC

OpenSPARC is an open source hardware project started in December 2005....
T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in VerilogVerilog Overview

Verilog is a hardware description language used to model electronic systems....
, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPLGNU General Public License

The GNU General Public License is a widely used free software license, originally written by Richard Stallman for the GNU p...
. Source based on existant open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License AgreementSoftware license agreement

A software license agreement is a memorandum of contract between a producer and a user of computer software which grants the...
.

S1S1 Core

S1 Core is an open source hardware microprocessor design developed by Simply RISC....
, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC v9 core capable of 4 way SMT. Like the T1, the source code is licensed under the GPLGNU General Public License

The GNU General Public License is a widely used free software license, originally written by Richard Stallman for the GNU p...
.

OpenSPARCOpenSPARC

OpenSPARC is an open source hardware project started in December 2005....
T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in VerilogVerilog

Verilog is a hardware description language used to model electronic systems....
, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPLGNU General Public License

The GNU General Public License is a widely used free software license, originally written by Richard Stallman for the GNU p...
. Source based on extant open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License AgreementSoftware license agreement

A software license agreement is a memorandum of contract between a producer and a user of computer software which grants the...
.

Supercomputers

As of November 2007, only one of the world's top 500TOP500

The TOP500 project ranks and details the 500 most powerful publicly-known computer systems in the world....
fastest supercomputers is based on SPARC64 processors:

Rank #392: Nagoya UniversityNagoya University

Nagoya University is a Japanese national university in Chikusa-ku, Nagoya, and is considered by some to be one of the most p...
Japan, PRIMEPOWER HPC2500 (1664 2.08 GHz processors), Fujitsu, 6860 GFLOPS

This list compares unfavorably with other processor architectures, which make up a much larger portion of the top 500TOP500

The TOP500 project ranks and details the 500 most powerful publicly-known computer systems in the world....
list. The SPARC processor family had 88 of the top 500 systems in June 2002, but has since lost popularity to faster chips from IBMIBM

company_name = International Business Machines Corporation |...
, Intel, and AMD.

External links

- a SPARC architecture specification extended with CMT, hyperprivileged mode, VIS 1, VIS 2, and so forth
(SuperSPARC, hyperSPARC)

SPARC

Features

History

SPARC64

SPARC microprocessor specifications

Operating system support

Open source implementations

Supercomputers

See also

External links