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Micro-operation
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In computer central processing units, micro-operations, also known as a micro-ops or 發ps, are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed macro-instructions in this context).
Various forms of 發ps have long been the basis for traditional microcode routines used to simplify the implementation of a particular CPU design or perhaps just the sequencing of certain multi-step operations or addressing modes.
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In computer central processing units, micro-operations, also known as a micro-ops or 發ps, are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed macro-instructions in this context).
Various forms of 發ps have long been the basis for traditional microcode routines used to simplify the implementation of a particular CPU design or perhaps just the sequencing of certain multi-step operations or addressing modes. More recently, 發ps have also been employed in a different way in order to let modern "CISC" processors more easily handle asynchronous parallel and speculative execution: As with traditional microcode, one or more table lookups (or equivalent) is done to locate the appropriate 發p-sequence based on the encoding and semantics of the machine instruction (the decoding or translation step), however, instead of having rigid 發p-sequences controlling the CPU directly from a microcode-ROM, 發ps are here dynamically issued, that is, buffered in rather long sequences before being executed.
This buffering means that the fetch and decode stages can be more detached from the execution units than is feasible in a more traditional microcoded (or "hard-wired") design. As this allows a degree of freedom regarding execution order, it makes some extraction of instruction level parallelism out of a normal single-threaded program possible (provided that dependencies are checked etc). It opens up for more analysis and therefore also for reordering of code sequences in order to dynamically optimize mapping and scheduling of 發ps onto machine resources (such as ALUs, load/store units etc). As this happens on the 發p-level, sub-operations of different machine (macro) instructions may often intermix in a particular 發p-sequence (forming partially reordered machine instructions).
Today, the optimization has gone even further; processors not only translate many machine instructions into a series of 發ps, but also do the opposite when appropriate; they combine certain machine instruction sequences (such as a compare followed by a conditional jump) into a more complex 發p which fits the execution model better and thus can be executed faster or with less machine resources involved.
Another way to try to improve performance is to cache the decoded micro-operations, so that if the same macroinstruction is executed again, the processor can directly access the decoded micro-operations from a special cache, instead of decoding them again. The Execution Trace Cache found in Intel's NetBurst Microarchitecture (Pentium 4) is so far the only widespread example of this technique. The size of this cache may be stated in terms of how many thousands of micro-operations it can store: k發ps.
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