Interrupt priority level
Encyclopedia
The interrupt priority level (IPL) is a part of the current system interrupt
state, which indicates the interrupt request
s that will currently be accepted. The IPL may be indicated in hardware by the registers in a Programmable Interrupt Controller
, or in software by a bitmask or integer value.
Assigning different priorities to interrupt requests can be useful in trying to balance system throughput versus interrupt latency
: some kinds of interrupts need to be responded to more quickly than others, but the amount of processing might not be large, so it makes sense to assign a higher priority to that kind of interrupt.
Control of interrupt level was also used to synchronize access to kernel data structures. Thus, the level-3 scheduler interrupt handler would temporarily raise IPL to 7 before accessing any actual scheduler data structures, then lower back to 3 before actually switching process contexts. However, it was not allowed for an interrupt handler to lower IPL below that at which it was entered, since to do so could destroy the integrity of the synchronization system.
Of course, multiprocessor
systems add their own complications, which are not addressed here.
Regardless of what the hardware might support, typical UNIX
-type systems only make use of two levels: the minimum (all interrupts enabled) and the maximum (all interrupts disabled).
computer and associated VMS
operating system supports 32 priority levels, from 0 to 31. Priorities 16 and above are for requests from external hardware, while values below 16 are available for software interrupts (used internally by the operating system to schedule its own activities). Not all values are actually used, but here are some of the more important ones:
Alpha
hardware contains native support for IPLs. When OpenVMS
was ported to Itanium
in 2001, the IPL scheme was simulated using features provided by the Itanium hardware.
Interrupt
In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
state, which indicates the interrupt request
Interrupt request
The computing phrase "interrupt request" is used to refer to either the act of interrupting the bus lines used to signal an interrupt, or the interrupt input lines on a Programmable Interrupt Controller...
s that will currently be accepted. The IPL may be indicated in hardware by the registers in a Programmable Interrupt Controller
Programmable Interrupt Controller
In computing, a programmable interrupt controller is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in...
, or in software by a bitmask or integer value.
Overview
An integer based IPL may be as small as a single bit, with just two values: 0 (all interrupts enabled) or 1 (all interrupts disabled). However, some architectures permit a greater range of values, where each value enables interrupt requests that specify a higher level, while blocking ones from the same or lower level.Assigning different priorities to interrupt requests can be useful in trying to balance system throughput versus interrupt latency
Latency (engineering)
Latency is a measure of time delay experienced in a system, the precise definition of which depends on the system and the time being measured. Latencies may have different meaning in different contexts.-Packet-switched networks:...
: some kinds of interrupts need to be responded to more quickly than others, but the amount of processing might not be large, so it makes sense to assign a higher priority to that kind of interrupt.
Control of interrupt level was also used to synchronize access to kernel data structures. Thus, the level-3 scheduler interrupt handler would temporarily raise IPL to 7 before accessing any actual scheduler data structures, then lower back to 3 before actually switching process contexts. However, it was not allowed for an interrupt handler to lower IPL below that at which it was entered, since to do so could destroy the integrity of the synchronization system.
Of course, multiprocessor
Multiprocessor
Computer system having two or more processing units each sharing main memory and peripherals, in order to simultaneously process programs.Sometimes the term Multiprocessor is confused with the term Multiprocessing....
systems add their own complications, which are not addressed here.
Regardless of what the hardware might support, typical UNIX
Unix
Unix is a multitasking, multi-user computer operating system originally developed in 1969 by a group of AT&T employees at Bell Labs, including Ken Thompson, Dennis Ritchie, Brian Kernighan, Douglas McIlroy, and Joe Ossanna...
-type systems only make use of two levels: the minimum (all interrupts enabled) and the maximum (all interrupts disabled).
OpenVMS IPLs
As an example of one of the more elaborate IPL-handling systems ever deployed, the VAXVAX
VAX was an instruction set architecture developed by Digital Equipment Corporation in the mid-1970s. A 32-bit complex instruction set computer ISA, it was designed to extend or replace DEC's various Programmed Data Processor ISAs...
computer and associated VMS
OpenVMS
OpenVMS , previously known as VAX-11/VMS, VAX/VMS or VMS, is a computer server operating system that runs on VAX, Alpha and Itanium-based families of computers. Contrary to what its name suggests, OpenVMS is not open source software; however, the source listings are available for purchase...
operating system supports 32 priority levels, from 0 to 31. Priorities 16 and above are for requests from external hardware, while values below 16 are available for software interrupts (used internally by the operating system to schedule its own activities). Not all values are actually used, but here are some of the more important ones:
- level 31 is for the "power-fail" interrupt.
- level 24 is for the clock interrupt. Note this is a higher priority than I/O interrupts.
- levels 20-23 are used for I/O devices.
- levels 8-11 are used for fork interrupts. When a driver receives a device interrupt (priority 20-23), it is supposed to do as little processing as possible at such a high priority; instead, if any time-consuming operations need to be done, these are to be deferred by requesting a software interrupt in the 8-11 range; when this interrupt is triggered, the further processing will resume. Similar to this are "bottom halves" and their successors in the LinuxLinuxLinux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
kernel. - level 7 is used to synchronize access to the process scheduler data structures.
- level 4 is used for I/O post-processing tasks—that is, final completion of a QIOQIOQIO is a term used in several computer operating systems designed by the former Digital Equipment Corporation of Maynard, Massachusetts.I/O operations on these systems are initiated by issuing a QIO call to the kernel...
request including returning results to the application process. - level 3 is used for the process rescheduling interrupt. Any code executing at higher interrupt levels is not allowed to assume that there was a current process context (since a process reschedule might be in progress). In particular, page faultPage faultA page fault is a trap to the software raised by the hardware when a program accesses a page that is mapped in the virtual address space, but not loaded in physical memory. In the typical case the operating system tries to handle the page fault by making the required page accessible at a location...
s are not allowed at this or higher levels. - level 2 is used to synchronize access to per-process data structures. Any time the kernel needs access to a process context, it sends that process a special kernel ASTAsynchronous System TrapAsynchronous system trap refers to a mechanism used in several computer operating systems designed by the former Digital Equipment Corporation of Maynard, Massachusetts....
which executes in the process context at IPL 2. - level 0 is the normal level for execution of non-interrupt code, including ordinary application code.
Alpha
DEC Alpha
Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer instruction set architecture developed by Digital Equipment Corporation , designed to replace the 32-bit VAX complex instruction set computer ISA and its implementations. Alpha was implemented in microprocessors...
hardware contains native support for IPLs. When OpenVMS
OpenVMS
OpenVMS , previously known as VAX-11/VMS, VAX/VMS or VMS, is a computer server operating system that runs on VAX, Alpha and Itanium-based families of computers. Contrary to what its name suggests, OpenVMS is not open source software; however, the source listings are available for purchase...
was ported to Itanium
Itanium
Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel markets the processors for enterprise servers and high-performance computing systems...
in 2001, the IPL scheme was simulated using features provided by the Itanium hardware.
See also
- InterruptInterruptIn computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
- Programmable Interrupt ControllerProgrammable Interrupt ControllerIn computing, a programmable interrupt controller is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in...
- spl (Unix)