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DEC Alpha
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Alpha, originally known as Alpha AXP, was a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace the 32-bit VAX complex instruction set computer (CISC) ISA and its implementations.
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Encyclopedia
Alpha, originally known as Alpha AXP, was a 64-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace the 32-bit VAX complex instruction set computer (CISC) ISA and its implementations. Alpha was implemented in microprocessors originally developed and fabricated by DEC. It was used in a variety of DEC workstations and servers, eventually forming the basis for almost all of their mid-to-upper-scale lineup. Several third-party vendors also produced Alpha systems, as well as PC compatible form factor motherboards.
Alpha supports both the OpenVMS (previously known as OpenVMS AXP) operating system and Tru64 UNIX (previously known as DEC OSF/1 AXP and Digital UNIX). Open source operating systems also run on the Alpha, notably Linux and BSD UNIX flavors (FreeBSD support ended as of 7.0). Microsoft supported the processor in Windows NT until NT 4.0 SP6 but did not extend Alpha support beyond RC1 of Windows 2000.
The Alpha architecture was sold, along with most parts of DEC, to Compaq in 1998. Compaq, already an Intel customer, decided to phase out Alpha in favor of the forthcoming Intel IA-64 "Itanium" architecture, and sold all Alpha intellectual property to Intel in 2001, effectively "killing" the product. Hewlett-Packard purchased Compaq later that same year, continuing development of the existing product line until 2004, and promising to continue selling Alpha-based systems, largely to the existing customer base, until October 2006 (later extended to April 2007).
History
Alpha was born out of an earlier RISC project named PRISM, itself the final product of several earlier projects. PRISM was cancelled after a proposal by the Palo Alto design team to build the Unix-only workstations (DECstation 3100) on a MIPS R2000 processor allowing the DECstation to come to market sooner. Among the differences between PRISM and other RISC processors, however, was that PRISM supported a user-programmable microcode known as Epicode. PRISM had been designed with the intent of releasing a new operating system along with it, known as Mica, which would allow it to run "native" programs at full speed while also supporting Digital's existing VMS programs from the VAX after minor conversion. DEC management doubted the need to produce a new computer architecture to replace their existing VAX and DECstation lines, and eventually killed the PRISM project in 1988.
By the time of cancellation, however, second-generation RISC chips (such as the newer SPARC architecture), were offering much better price/performance ratios than the VAX lineup. It was clear a third generation would completely outperform the VAX in all ways, not just on cost. Another study was started to see if a new RISC architecture could be defined that could directly support the VMS operating system. The new design used most of the basic PRISM concepts, but was re-tuned to allow VMS and VMS programs to run at reasonable speed with no conversion at all. The decision was also made to upgrade the design to a full 64-bit implementation from PRISM's 32-bit, a conversion all of the major RISC vendors were undertaking. Eventually that new architecture became Alpha. The primary Alpha instruction set architects were Richard L. Sites and Richard T. Witek. The PRISM's Epicode was developed into the Alpha's PALcode, providing an abstracted interface to platform- and processor implementation-specific features.
The main contribution of Alpha to the microprocessor industry, and the main reason for its excellent performance, was not so much the architecture but rather superb implementation. At that time (as it is now), the microchip industry was dominated by automated design and layout tools. The chip designers at Digital continued pursuing sophisticated manual circuit design in order to deal with the overly complex VAX architecture. The Alpha chips showed that manual circuit design applied to a simpler, cleaner architecture allowed for much higher operating frequencies than those that were possible with the more automated design systems. These chips caused a renaissance of custom circuit design within the microprocessor design community.
Originally, the Alpha processors were designated the DECchip 21x64 series, with "DECchip" replaced in the mid-1990s with "Alpha". The first two digits, "21" signifies the 21st century, and the last two digits, "64" signifies 64 bits. The middle digit corresponded to the generation of the Alpha architecture. Internally, Alpha processors were also identified by EV numbers, EV officially standing for "Extended VAX" but having an alternative humorous meaning of "Electric Vlasic", giving homage to the Electric Pickle experiment at Western Research Lab .
The first few generations of the Alpha chips were some of the most innovative of their time. The first version, the Alpha 21064 or EV4, was the first CMOS microprocessor whose operating frequency rivalled higher-powered ECL minicomputers and mainframes. The second, 21164 or EV5, was the first microprocessor to place a large secondary cache on chip. The third, 21264 or EV6, was the first microprocessor to combine both high operating frequency and the more complicated out-of-order execution microarchitecture. The 21364 or EV7 was the first high performance processor to include an Integrated Memory Controller. The unproduced EV8 would have been the first to include simultaneous multithreading, but this version was caught up in the sale to Compaq. The Tarantula research project, which most likely would have been called EV9, would have been the first processor to feature a powerful vector core.
A persistent report attributed to DEC insiders suggests the choice of the AXP tag for the processor was made by DEC's legal department, which was still smarting from the VAX trademark fiasco. After a lengthy search the tag "AXP" was found to be entirely unencumbered. Within the computer industry, a joke got started that the acronym AXP meant "Almost Exactly PRISM".
Architecture
Data types
In the Alpha architecture, a byte was defined as an 8-bit datum, a word as a 16-bit datum, a longword as a 32-bit datum, a quadword as a 64-bit datum and an octaword as a 128-bit datum.
The Alpha architecture originally defined six data types:
- Quadword (64-bit) integer
- Longword (32-bit) integer
- IEEE T-floating-point (double precision, 64-bit)
- IEEE S-floating-point (single precision, 32-bit)
To maintain a level of compatibility with VAX, the 32-bit architecture the Alpha succeeded, two VAX data types were included:
- VAX G-floating point (double precision, 64-bit)
- VAX F-floating point (single precision, 32-bit)
The Alpha had some provision for future expansion of the instruction set to include 128-bit data types.
Instruction formats
Integer operate, register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | Opcode | Ra | Rb | Unused | 0 | Function | Rc | |
The integer operate format is used by integer instructions. It contains a 6-bit opcode field, followed by the Ra field, which specifies the register containing the first operand and the Rb field, specifies the register containing the second operand. Next is a 3-bit field which is unused and reserved. A 1-bit field contains a "0", which distinguished this format from the integer literal format. A 7-bit function field follows, which is used in conjunction with the opcode to specify an operation. The last field is the Rc field, which specifies the register which the result of a computation should be written to. The register fields are all 5 bits long, required to address 32 unique locations, the 32 integer registers.
Integer operate, literal
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | Opcode | Ra | Literal | 1 | Function | Rc | |
The integer literal format is used by integer instructions which use a literal as one of the operands. The format is the same as the integer operate format except for the replacement of the 5-bit Rb field and the 3 bits of unused space with an 8-bit literal field.
Floating-point operate
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | Opcode | Ra | Rb | Function | Rc | |
The floating-point operate format is used by floating-point instructions. It is similar to the integer operate format, but has a 11-bit function field made possible by using the literal and unsed bits which are reserved in integer operate format.
Memory
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | Opcode | Ra | Rb | Displacement | |
The memory format is used by mostly by load and store instructions. It has a 6-bit opcode field, a 5-bit Ra field, a 5-bit Rb field and a 16-bit displacement field.
Branch
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | Opcode | Ra | Displacement | |
Branch instructions have a 6-bit opcode field, a 5-bit Ra field and a 21-bit displacement field. The Ra field specifies a register to be tested by a conditional branch instruction, and if the condition is met, the program counter is updated by adding the contents of the displacement field with the program counter. The displacement field contains a signed integer and if the value of the integer is positive, if the branch is taken then the program counter is incremented. If the value of the integer is negative, then program counter is decremented if the branch is taken. The range of a branch is 1,048,576. The Alpha Architecture was designed with a large range as part of the architecture's forward-looking goal.
CALL_PAL
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | Opcode | Function | |
The CALL_PAL format is used by the CALL_PAL instruction, which is used to call PALcode subroutines. The format retains the opcode field but replaces the others with a 26-bit function field, which contains an integer specifying a PAL subroutine.
Implementations
At the time of its announcement, Alpha was heralded as an architecture for the next 25 years. While this was not to be, Alpha has nevertheless had a reasonably long life. The first version, the Alpha 21064 (otherwise known as the EV4) was introduced in November 1992 running at up to 192 MHz; a slight shrink of the die (the EV4S, shrunk from 0.75 µm to 0.675 µm) ran at 200 MHz a few months later. The 64-bit processor was a superpipelined and superscalar design, like other RISC designs, but nevertheless outperformed them all and DEC touted it as the world's fastest processor. Careful attention to circuit design, a hallmark of the Hudson design team, like a huge centralized clock circuitry, allowed them to run the CPU at higher speeds, even though the microarchitecture was fairly similar to other RISC chips. In comparison, the less expensive Intel Pentium ran at 66 MHz when it was launched the following spring.
The Alpha 21164 or EV5 became available in 1995 at processor frequencies of up to 333 MHz. In July 1996 the line was speed bumped to 500 MHz, in March 1998 to 666 MHz. Also in 1998 the Alpha 21264 (EV6) was released at 450 MHz, eventually reaching (in 2001 with the 21264C/EV68CB) 1.25 GHz. In 2003, the Alpha 21364 or EV7 Marvel was launched, essentially an EV68 core with four 1.6 GB/s inter-processor communication links for improved multiprocessor system performance, running at 1 or 1.15 GHz. Around 500,000 Alpha based systems were sold by the end of 2000.
In 1999, the production of Alpha chips was licensed to Samsung Electronics Company. Following the purchase of Digital by Compaq the majority of the Alpha products were placed with API NetWorks, Inc. (previously Alpha Processor Inc.), a private company funded by Samsung and Compaq. In October 2001, Microway became the exclusive sales and service provider of API NetWorks' Alpha-based product line.
On June 25 2001, Compaq announced that Alpha would be phased out by 2004 in favor of Intel's Itanium, canceled the planned EV8 chip, and sold all Alpha intellectual property to Intel. HP, new owner of Compaq later the same year, announced that development of the Alpha series would continue for a few more years, including the release of a 1.3 GHz EV7 variant called the EV7z. This would be the final iteration of Alpha, the 0.13 µm EV79 also being canceled. HP stopped selling AlphaServers with OpenVMS and Tru64 UNIX on April 27 2007, and has promised support until at least 2012.
Ironically, in mid-2003, as the Alpha was about to be phased out, the fastest and second fastest computers (in 2002) in the United States were both implemented using Alpha processors (in the case of the former, a ).
Model history
| Model | Model number | Year | Frequency [MHz] | Process [µm] | Transistors [millions] | Die size [mm²] | IO Pins | Power [W] | Voltage | Dcache [KB] | Icache [KB] | Scache | Bcache | ISA |
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| EV4 | 21064 | 1992 | 100–192 | 0.75 | 1.68 | 234 | 290 | 30 | 3.3 | 8 | 8 | – | 128 KB-8 MB | |
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| EV4S | 21064 | 1993 | 200 | 0.675 | 1.68 | | 290 | | 3.3 | 8 | 8 | – | 128 KB-8 MB |
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| EV45 | 21064A | 1994 | 200–300 | 0.5 | 2.85 | 164 | | 33 | 3.3 | 16 | 16 | – | | |
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| LCA4 | 21066 | 1993 | 100–166 | 0.675 | 1.75 | 209 | | 21 | 3.3 | 8 | 8 | – | | |
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| LCA4 | 21066 | 1994 | 200 | 0.5 | 1.75 | 209 | | 21 | 3.3 | 8 | 8 | – | | |
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| LCA4 | 21068 | 1994 | 66 | 0.675 | 1.75 | 209 | | 9 | 3.3 | 8 | 8 | – | | |
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| LCA45 | 21066A | 1994 | 100–266 | 0.5 | 1.8 | 161 | | 23 | 3.3 | 8 | 8 | – | | |
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| LCA45 | 21068A | 1994 | 100 | 0.5 | 1.8 | 161 | | | 3.3 | 8 | 8 | – | | |
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| EV5 | 21164 | 1995 | 266–500 | 0.5 | 9.3 | 299 | 296 | 56 | 3.3/2.5 | 8 | 8 | 96 KB | 1 | R |
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| EV56 | 21164A | 1996 | 366–666 | 0.35 | 9.66 | 209 | | 31–55 | 3.3/2.5 | 8 | 8 | 96 KB | 1–2 MB | R,B |
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| PCA56 | 21164PC | 1997 | 400–533 | 0.35 | 3.5 | 141 | 264 | 40 | 3.3/2.5 | 8 | 16 | – | 512 KB–4 MB | R,B,M |
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| PCA57 | 21164PC | | 600–666 | 0.28 | 5.7 | 101 | 283 | 20 | 2.5/2.0 | 16 | 32
| – | 512 KB–4 MB | R,B,M |
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| EV6 | 21264 | 1998 | 450–600 | 0.35 | 15.2 | 314 | 389 | 73 | 2.0 | 64 | 64 | – | 2–8 MB | R,B,M,F |
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| EV67 | 21264A | 1999 | 667–750 | 0.25 | 15.2 | 210 | 389 | | 2.0 | 64 | 64 | – | 2–8 MB | R,B,M,F,C |
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| EV68AL | 21264B | 2001 | 800–833 | 0.18 | 15.2 | 125 | | | 1.7 | 64 | 64 | – | 2–8 MB | R,B,M,F,C,T |
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| EV68CB | 21264C | 2001 | 1000–1250 | 0.18 | 15.2 | 125 | | 65–75 | 1.65 | 64 | 64 | – | 2–8 MB | R,B,M,F,C,T |
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| EV68CX | 21264D | | | | | | | | 1.65 | 64 | 64 | – | 2–8 MB | R,B,M,F,C,T |
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| EV7 | 21364 | 2003 | 1000–1150 | 0.18 | 130 | 397 | 1443 | 125 | 1.5 | 64 | 64 | 1.75 MB | – | R,B,M,F,C,T |
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| EV7z | 21364 | 2004 | 1300 | 0.18 | 130 | 397 | 1443 | 125 | 1.5 | 64 | 64 | 1.75 MB | – | R,B,M,F,C,T |
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| Cancelled |
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| EV78/EV79 | 21364A | (cancelled — was to be 2004) | 1700 | 0.13 | 152 | 300 | 1443 | 120 | 1.2 | 64 | 64 | 1.75 MB | – | R,B,M,F,C,T |
|---|
| EV8 | 21464 | (cancelled — was to be 2003) | 1200–2000 | 0.125 | 250 | 350? | 1800 | ?? | 1.2 | 64 | 64 | 3–4 MB? | – | R,B,M,F,C,T |
|---|
| Model | Model number | Year | Frequency [MHz] | Process [µm] | Transistors [millions] | Die size [mm²] | IO Pins | Power [W] | Voltage | Dcache [KB] | Icache [KB] | Scache | Bcache | ISA |
|---|
ISA extensions:
- R – ?
- B – BWX, the "Byte/Word Extension", adding instructions to allow 8- and 16-bit operations from memory and I/O
- M – MVI, "multimedia" instructions
- F – FIX, instructions to move data between integer and floating point registers and for square root
- C – CIX, instructions for counting and finding bits
- T – Support for prefetch with modify intent to improve the performance of the first attempt to acquire a lock
Performance
To get an idea of the performance of Alpha-based systems, here are some SPEC performance numbers (SPEC92, SPEC95). Note that the SPEC results report the measured performance of a whole computer system (CPU, bus, memory, compiler optimizer), not just the CPU. Also note that the benchmark and scale changed from 1992 to 1995. However, the idea here is to give a rough idea of the Alpha architecture performance compared with Intel-based offerings at the same time. Perhaps the most obvious trend is that while Intel could always get reasonably close to Alpha in integer performance, in floating point performance the difference was considerable.
| System | CPU | MHz | integer | floating point |
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1995 Performance comparison (using int92 and fp92) | AlphaServer 8400 5/350 | 21164 (EV5) | 350 | 432.8 | 602.2 |
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| Adler | Pentium Pro | 200 | 366.0 | 283.2 |
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| System | CPU | MHz | integer | floating point |
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2000 Performance comparison (using int2000 and fp2000) | AlphaServer ES40 6/833 | 21264 (EV6) | 833 | 50.0 | 100.0 |
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| Intel VC820 motherboard | Pentium III | 1000 | 46.8 | 31.9 |
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Alpha-based systems
The first generation of DEC Alpha-based systems comprised the DEC 3000 AXP series workstations and low-end servers, DEC 4000 AXP series mid-range servers, and DEC 7000 AXP and 10000 AXP series high-end servers. The DEC 3000 AXP systems used the same TURBOchannel bus as the previous MIPS-based DECstation models, whereas the 4000 was based on FutureBus+ and the 7000/10000 shared an architecture with corresponding VAX models.
DEC also produced a PC-like Alpha workstation with an EISA bus, the DECpc AXP 150 (codename "Jensen", also known as the DEC 2000 AXP). This was the first Alpha system to support Windows NT. DEC later produced Alpha versions of their Celebris XL and Digital Personal Workstation PC lines, with 21164 processors.
Digital also produced single board computers based on the VMEbus for embedded and industrial use. The first generation included the 21068-based AXPvme 64 and AXPvme 64LC, and the 21066-based AXPvme 160. These were introduced on March 1, 1994. Later models such as the AXPvme 100, AXPvme 166 and AXPvme 230 were based on the 21066A processor, while the Alpha VME 4/224 and Alpha VME 4/288 were based on the 21064A processor. The last models, the Alpha VME 5/352 and Alpha VME 5/480, were based on the 21164 processor.
The 21066 chip was used in the DEC Multia VX40/41/42 compact workstation and the ALPHAbook 1 laptop from Tadpole Technology.
In 1994, DEC launched a new range of AlphaStation and AlphaServer systems. These used 21064 or 21164 processors and introduced the PCI bus, VGA-compatible frame buffers and PS/2-style keyboards and mice. The AlphaServer 8000 series superseded the DEC 7000/10000 AXP and also employed XMI and FutureBus+ buses.
The AlphaStation XP1000 was the first workstation based on the 21264 processor. Later AlphaServer/Station models based on the 21264 were categorised into DS (departmental server), ES (enterprise server) or GS (global server) families.
The final 21364 chip was used in the AlphaServer ES47, ES80 and GS1280 models and the AlphaStation ES47.
A number of OEM motherboards was produced by DEC, such as the 21066 and 21068-based AXPpci 33 "NoName", which was part of a major push into the OEM market by the company, the 21164-based AlphaPC 164 and AlphaPC 164LX, the 21164PC-based AlphaPC 164SX and AlphaPC 164RX and the 21264-based AlphaPC 264DP. Several third-parties such as Samsung and API also produced OEM motherboards such as the API UP1000 and UP2000.
To assist third parties in developing hardware and software for the platform, DEC produced Evaluation Boards, such as the EB64+ and EB164 for the Alpha 21064A and 21164 microprocessors respectively.
The 21164 and 21264 processors were used by NetApp in various Network Attached Storage systems, while the 21064 and 21164 processors were used by Cray in their T3D and T3E massively parallel supercomputers.
Supercomputers
The fastest supercomputers based on Alpha processors:
- ASCI Q at Los Alamos National Laboratory. Machine: HP AlphaServer SC45/GS Cluster. CPU: 4096 Alpha (1.25 GHz). Rmax: 7.727 Teraflops.
External links
Documents from Digital
- This issue contains several articles from Alpha's Architects
- This link features the hardware reference manuals and datasheets for Alpha microprocessors, chipsets and OEM motherboards. Includes the Alpha Architecture Handbook and various programming manuals.
AlphaServer News Sites
- Tru64 UNIX on Alpha
- OpenVMS on Alpha
Free Operating Systems for Alpha
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- As of FreeBSD 7.0, support for the Alpha platform will be removed. FreeBSD/alpha support will continue in maintenance mode for future FreeBSD 6.x releases.
- free non-commercial licenses for OpenVMS, and low-cost media
Emulators for Alpha
Other Sources
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