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Explicitly Parallel Instruction Computing
 
 
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Explicitly Parallel Instruction Computing (EPIC) is a term coined in 1997 by the HP-Intel alliance
Itanium

Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel has released two processor families using the brand: the original Itanium and the Itanium 2....
 to describe a computing paradigm that began to be researched in the early 1980s. This paradigm is also called Independence architectures. It was the basis for Intel and HP
Hewlett-Packard

The Hewlett-Packard Company , commonly referred to as HP, is a technology corporation headquartered in Palo Alto, California, United States....
 development of the Intel Itanium
Itanium

Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel has released two processor families using the brand: the original Itanium and the Itanium 2....
 architecture, and HP later asserted that "EPIC" was merely an old term for the Itanium architecture.






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Explicitly Parallel Instruction Computing (EPIC) is a term coined in 1997 by the HP-Intel alliance
Itanium

Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel has released two processor families using the brand: the original Itanium and the Itanium 2....
 to describe a computing paradigm that began to be researched in the early 1980s. This paradigm is also called Independence architectures. It was the basis for Intel and HP
Hewlett-Packard

The Hewlett-Packard Company , commonly referred to as HP, is a technology corporation headquartered in Palo Alto, California, United States....
 development of the Intel Itanium
Itanium

Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel has released two processor families using the brand: the original Itanium and the Itanium 2....
 architecture, and HP later asserted that "EPIC" was merely an old term for the Itanium architecture. EPIC permits microprocessors to execute software instructions in parallel by using the compiler
Compiler

A compiler is a computer program that transforms source code written in a programming language into another computer language . The most common reason for wanting to transform source code is to create an executable program....
, rather than complex on-die
Die (integrated circuit)

A die in the context of integrated circuits is a small block of semiconducting material, on which a given functional circuit is fabricated.Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon through processes such as photolithography....
 circuitry, to control parallel instruction execution. This was intended to allow simple performance scaling without resorting to higher clock frequencies
Clock rate

The clock rate is the fundamental rate in cycles per second for the frequency of the clock in any synchronous circuit. For example, a crystal oscillator frequency reference typically is synonymous with a fixed sinusoidal waveform, a clock rate is that frequency reference translated by electronic circuitry into a corresponding square wav...
.

Roots in VLIW

By 1989, researchers at HP recognized that RISC architectures were reaching a limit at one instruction per cycle. They began an investigation into a new architecture, later named EPIC. The basis for the research was VLIW
Very long instruction word

Very Long Instruction Word or VLIW refers to a Central processing unit architecture designed to take advantage of instruction level parallelism ....
, in which multiple operations are encoded in every instruction, and then processed by multiple execution units.

One goal of EPIC was to move the complexity of instruction scheduling from the CPU hardware to the software compiler, which can do the instruction scheduling statically (with help of trace feedback information). This eliminates the need for complex scheduling circuitry in the CPU, which frees up space and power for other functions, including additional execution resources. An equally important goal was to further exploit instruction level parallelism
Instruction level parallelism

Instruction-level parallelism is a measure of how many of the operations in a computer program can be performed simultaneously. Consider the following program:...
 (ILP), by using the compiler to find and exploit additional opportunities for parallel execution
Parallel computing

Parallel computing is a form of computing in which many calculations are carried out simultaneously, operating on the principle that large problems can often be divided into smaller ones, which are then solved Concurrency ....
.

VLIW (at least the original forms) has several short-comings that precluded it from becoming mainstream:
  • VLIW instruction set
    Instruction set

    An instruction set is a list of all the instruction , and all their variations, that a processor can execute.Instructions include:* Arithmetic such as add and subtract...
    s are not backward compatible
    Backward compatibility

    In technology, for example in telecommunications and computing, a device or technology is said to be backwards compatible if it allows input generated by older devices....
     between implementations. When wider implementations (more execution unit
    Execution unit

    In computer engineering, an execution unit is a part of a central processing unit that performs the operations and calculations called for by the computer program....
    s) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.
  • Load responses from a memory hierarchy which includes CPU cache
    CPU cache

    A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access computer storage. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations....
    s and DRAM
    Dram

    Dram or DRAM may refer to:* Dram , an imperial unit of mass and volume* Armenian dram, a monetary unit* Dynamic random access memory* Database of Recorded American Music...
     do not have a deterministic delay. This makes static scheduling of load instructions by the compiler very difficult.


Moving beyond VLIW

EPIC architectures add several features to get around the deficiencies of VLIW:
  • Each group of multiple software instructions is called a bundle. Each of the bundles has information indicating if this set of operations is depended upon by the subsequent bundle. With this capability, future implementations can be built to issue multiple bundles in parallel. The dependency information is calculated by the compiler, so the hardware does not have to perform operand dependency checking.
  • A speculative load instruction is used as a type of data prefetch. This prefetch increases the chances for a primary cache hit for normal loads.
  • A check load instruction also aids speculative loads by checking that a load was not dependent on a previous store.


The EPIC architecture also includes a grab-bag of architectural concepts to increase ILP:
  • Predicated execution
    Branch predication

    Branch predication is a strategy in computer architecture design for mitigating the costs usually associated with conditional branch es, particularly branches to short sections of code....
     is used to decrease the occurrence of branches and to increase the speculative execution
    Speculative execution

    In computer science, speculative execution is the execution of Code , the result of which may not be needed. In the context of functional programming, the term "speculative evaluation" is used instead....
     of instructions. In this feature, branch conditions are converted to predicate registers which are used to kill results of executed instructions from the side of the branch which is not taken.
  • Delayed exceptions (using a Not-A-Thing bit within the general purpose registers) also allow more speculative execution past possible exceptions.
  • Very large architectural register file
    Register file

    A register file is an array of processor registers in a central processing unit. Modern integrated circuit-based register files are usually implemented by way of fast static RAMs with multiple ports....
    s avoid the need for register renaming
    Register renaming

    In computer engineering, register renaming refers to a technique usedto avoid unnecessary serialization of program operations imposed by the reuse...
    .
  • Multi-way branch instructions


The Itanium
Itanium

Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel has released two processor families using the brand: the original Itanium and the Itanium 2....
 architecture also added register renaming
Register renaming

In computer engineering, register renaming refers to a technique usedto avoid unnecessary serialization of program operations imposed by the reuse...
 - a digital signal processing
Digital signal processing

Digital signal processing is concerned with the representation of the signal s by a sequence of numbers or symbols and the processing of these signals....
 concept useful for loop unrolling and software pipelining
Software pipelining

In computer science, software pipelining is a technique used to Optimization Control flow#Loops, in a manner that parallels Instruction pipeline....
.

Other research and development

There have been other investigations into EPIC architectures that are not directly tied to the development of the Itanium architecture.
  • The IMPACT project at University of Illinois at Urbana-Champaign
    University of Illinois at Urbana-Champaign

    The University of Illinois at Urbana-Champaign is a public university research university in the state of Illinois, United States. It is the oldest and largest campus in the University of Illinois system....
    , led by Wen-mei Hwu
    Wen-mei Hwu

    Wen-mei Hwu is a professor at University of Illinois at Urbana-Champaign specializing in compiler design, computer architecture, Microarchitecture, and parallel processing....
    , was the source of much influential research on this topic.
  • The PlayDoh architecture from HP-labs was another major research project.
  • Gelato
    Gelato Federation

    The Gelato Federation is a "global technical community dedicated to advancing Linux on the Intel Itanium platform through collaboration, education, and leadership." Formed in 2001, membership includes more than seventy academic and research organizations around the world, including several that operate Itanium-based supercomputers on the Top...
     is an open source development community in which academic and commercial researchers are working to develop more effective compilers for Linux applications running on Itanium servers.


See also

  • Complex instruction set computer
    Complex instruction set computer

    A complex instruction set computer is a computer instruction set architecture in which each instruction can execute several low-level operations, such as a load from Memory , an arithmetic operator, and a memory , all in a single instruction....
     (CISC)
  • Reduced instruction set computer
    Reduced instruction set computer

    The acronym RISC , for reduced instruction set computing, represents a CPU design strategy emphasizing the insight that simplified instructions that "do less" may still provide for higher performance if this simplicity can be utilized to make instructions execute very quickly....
     (RISC)
  • Very long instruction word
    Very long instruction word

    Very Long Instruction Word or VLIW refers to a Central processing unit architecture designed to take advantage of instruction level parallelism ....
     (VLIW)
  • Russian processors "Elbrus"
    Elbrus (computer)

    Elbrus is a series of Soviet Union supercomputer systems developed by Lebedev Institute of Precision Mechanics and Computer Engineering since the 1970s....


External links

  • Mark Smotherman (2002) ""