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In computer architecture
Computer architecture

Computer architecture in computer engineering is the conceptual design and fundamental operational structure of a computer system. It is a blueprint and functional description of requirements and design implementations for the various parts of a computer, focusing largely on the way by which the central processing unit performs internally an...
, Cycles per instruction (clock cycles per instruction or clocks per instruction or CPI) is a term used to describe one aspect of a processor's
Central processing unit

A central processing unit is an electronic circuit that can execute computer programs. This broad definition can easily be applied to many early computers that existed long before the term "CPU" ever came into widespread usage....
 performance: the number of clock cycles that happen when an instruction
Instruction (computer science)

In computer science, an instruction is a single operation of a central processing unit defined by an instruction set architecture. In a broader sense, an "instruction" may be any representation of an element of an executable program, such as a bytecode....
 is being executed. It is the multiplicative inverse
Multiplicative inverse

In mathematics, a multiplicative inverse or reciprocal for a number x, denoted by 1⁄x or x −1, is a number which when multiplied by x yields the multiplicative identity, 1....
 of Instructions Per Cycle
Instructions Per Cycle

In computer architecture, Instructions Per Clock is a term used to describe one aspect of a central processing unit's performance: the average number of instruction s executed for each clock cycle....
.

us assume a Classic RISC pipeline
Classic RISC pipeline

In the history of computer hardware, some early reduced instruction set computer central processing units used a very similar architectural solution, now called a classic RISC pipeline....
, with the following 5 stages:
1) Instruction fetch cycle (IF)
2) Instruction decode cycle (ID)
3) Execution cycle (EX)
4) Memory access (MEM)
5) Write-back cycle (WB)


Each stage requires one clock cycle and an instruction passes through the stages sequentially.






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In computer architecture
Computer architecture

Computer architecture in computer engineering is the conceptual design and fundamental operational structure of a computer system. It is a blueprint and functional description of requirements and design implementations for the various parts of a computer, focusing largely on the way by which the central processing unit performs internally an...
, Cycles per instruction (clock cycles per instruction or clocks per instruction or CPI) is a term used to describe one aspect of a processor's
Central processing unit

A central processing unit is an electronic circuit that can execute computer programs. This broad definition can easily be applied to many early computers that existed long before the term "CPU" ever came into widespread usage....
 performance: the number of clock cycles that happen when an instruction
Instruction (computer science)

In computer science, an instruction is a single operation of a central processing unit defined by an instruction set architecture. In a broader sense, an "instruction" may be any representation of an element of an executable program, such as a bytecode....
 is being executed. It is the multiplicative inverse
Multiplicative inverse

In mathematics, a multiplicative inverse or reciprocal for a number x, denoted by 1⁄x or x −1, is a number which when multiplied by x yields the multiplicative identity, 1....
 of Instructions Per Cycle
Instructions Per Cycle

In computer architecture, Instructions Per Clock is a term used to describe one aspect of a central processing unit's performance: the average number of instruction s executed for each clock cycle....
.

Explanation

Let us assume a Classic RISC pipeline
Classic RISC pipeline

In the history of computer hardware, some early reduced instruction set computer central processing units used a very similar architectural solution, now called a classic RISC pipeline....
, with the following 5 stages:
1) Instruction fetch cycle (IF)
2) Instruction decode cycle (ID)
3) Execution cycle (EX)
4) Memory access (MEM)
5) Write-back cycle (WB)


Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without Pipelining, a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5. Therefore without pipelining the number of cycles it takes to execute an instruction is 5. This is the definition of CPI.

With pipelining we can improve the CPI by exploiting Instruction level parallelism
Instruction level parallelism

Instruction-level parallelism is a measure of how many of the operations in a computer program can be performed simultaneously. Consider the following program:...
. For example, what if an instruction is fetched every cycle? We could theoretically have 5 instructions in the 5 pipeline stages at once (one instruction per stage). In this case, a different instruction would complete stage 5 in every clock cycle, and therefore on average we have one clock cycle per instruction (CPI = 1).

With a single issue processor, the best CPI attainable is 1. However with multiple issue processors, we may achieve even better CPI values. For example a processor that issues two instructions per clock cycle (see Superscalar
Superscalar

A superscalar Central processing unit architecture implements a form of parallel computer called instruction level parallelism within a single processor....
 processors) can achieve a CPI of 0.5 when two instructions are completing every clock cycle.

Calculations


Multi-cycle Example

For the multi-cycle MIPS, there are 5 types of instructions:
  • Load (5 cycles)
  • Store (4 cycles)
  • R-type (4 cycles)
  • Branch (3 cycles)
  • Jump (3 cycles)


If a program has
  • 50% R-type instructions
  • 15% Load instructions
  • 25% Store instructions
  • 8% Branch instructions
  • 2% Jump instructions


Then, the CPI is: CPI = (4 x 50 + 5 x 15 + 4 x 25 + 3 x 8 + 3 x 2) / 100 = 4.05

Example

40-MHz processor was used to execute a benchmark program with the following instruction mix and clock cycle count:
Instruction Type Instruction count Clock cycle count
Integer arithmetic 45000 1
Data transfer320002
Floating point 150002
Control transfer80002


Determine the effective CPI, MIPS
MIPS architecture

MIPS is a RISC instruction set architecture developed by MIPS Technologies . In the mid to late 1990s, it was estimated that one in three RISC microprocessors produced were MIPS implementations....
 rate, and execution time for this program.

total instruction count = 100000

CPI = (45000*1 + 32000*2 + 15000*2 + 8000*2)/100000 = 1550000/100000 = 1.55

MIPS = clock frequency/(CPI*1000000) = (40*1000000)/(1.55*1000000) = 25.8

Execution time (T) = CPI*Instruction count*clock time = CPI*Instruction count/frequency = 1.55*100000/40000000 = 1.55/400 = 3.87 ms Ans.

See also

  • Instructions Per Cycle
    Instructions Per Cycle

    In computer architecture, Instructions Per Clock is a term used to describe one aspect of a central processing unit's performance: the average number of instruction s executed for each clock cycle....