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Blackfin

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Encyclopedia
The Blackfin is a family of 16- or 32-bit microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...

s developed, manufactured and marketed by Analog Devices
Analog Devices
Analog Devices, Inc. , known as ADI, is an American multinational semiconductor company specializing in data conversion and signal conditioning technology, headquartered in Norwood, Massachusetts...

. The family is characterized by their built-in, fixed-point digital signal processor
Digital signal processor
A digital signal processor is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing.-Typical characteristics:...

 (DSP) functionality supplied by 16-bit Multiply–accumulates (MACs), accompanied on-chip by a small and power-efficient microcontroller
Microcontroller
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM...

. The result is a low-power
Low-power
In electronics, the term low-power may mean:* Low-power broadcasting, that the power of the broadcast is less, i.e. the radio waves are not intended to travel as far as from typical transmitters....

, unified processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding . There are several hardware development kits for the Blackfin. Open-source operating systems for the Blackfin include uClinux
UClinux
μClinux stands for "MicroController Linux," and is pronounced "you-see-Linux" as explained on the website, not the way the Greek letter mu is normally pronounced. It was a fork of the Linux kernel for microcontrollers without a memory management unit...

.

Architecture Details


Blackfin processors use a 32-bit
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....

 RISC
Reduced instruction set computer
Reduced instruction set computing, or RISC , is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer...

 microcontroller
Microcontroller
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM...

 programming model on a SIMD
SIMD
Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...

 architecture, which was co-developed by Intel and Analog Devices
Analog Devices
Analog Devices, Inc. , known as ADI, is an American multinational semiconductor company specializing in data conversion and signal conditioning technology, headquartered in Norwood, Massachusetts...

, as MSA (Micro Signal Architecture).

The Blackfin processor architecture was announced in December, 2000 and first demonstrated at the Embedded Systems Conference
Embedded Systems Conference
The Embedded Systems Conference is a conference and expo that takes place in six locations around the world. ESC is the largest gathering for System Architects and Design Engineers, focusing on networking, innovation and training...

 in June, 2001.

The Blackfin architecture incorporates aspects of ADI's older SHARC
Super Harvard Architecture Single-Chip Computer
The Super Harvard Architecture Single-Chip Computer is a high performance floating-point and fixed-point DSP from Analog Devices,...

 architecture and Intel's XScale
XScale
The XScale, a microprocessor core, is Intel's and Marvell's implementation of the ARMv5 architecture, and consists of several distinct families: IXP, IXC, IOP, PXA and CE . Intel sold the PXA family to Marvell Technology Group in June 2006....

 architecture into a single core, combining digital signal processing (DSP) and microcontroller functionality. There are many differences in the core architecture between Blackfin/MSA and XScale/ARM or SHARC, but the combination provides improvements in performance, programmability and power consumption over traditional DSP or RISC architecture designs.

The Blackfin architecture encompasses various CPU models, each targeting particular applications. Analog Devices keeps a comprehensive list of products. The Blackfin family is summarized in the following table.

Blackfin Processor Family Selection Table

|Proc-
essor
ADSP-
|Max
Clock
MHz
(Cores)
|L1
Inst
SRAM
(Cache)
KB
|L1
Data
SRAM
(Cache)
Scratch
KB
|L2
Mem
|L3
Boot
ROM
KB
|Int
Flash
MB
(Serial
/Par)
(Exec-
utable)
|Ext
SDRAM
(Async
/Mobile)
E
x
t

D
D
R
A
s
y
n
c
,
M
o
b
i
l
e
|N
A
N
D

F
l
a
s
h
|G
P
I
O
|T
i
m
e
r
s
|U
A
R
T
|S
P
O
R
T
|P
P
I
|S
P
I
|I
2
C
/
T
W
I
|C
A
N
|E
N
E
T

M
A
C
|P
i
x
e
l
C
o
m
p
|U
S
B

2
.
0
(
O
T
G
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|C
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S
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u
r
i
t
y
|H
o
s
t
D
M
A
|A
T
A
P
I
|S
D
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S
D
I
O
|S
t

C
o
d
e
c
|M
X
V
R
|EZLITE
(EZBRD
/STAMP)
BF506F SubSet
BF504 400 32 (16) 32 (16) 4 4 - - - - 35 8GP, 1 WD 2 2 1 2 1 1 - - - - - - Y - - BF506F (N/N)
BF504F 400 32 (16) 32 (16) 4 4 4 (P)(E) - - - 35 8GP, 1 WD 2 2 1 2 1 1 - - - - - - Y - - BF506F (N/N)
BF506F 400 32 (16) 32 (16) 4 4 4 (P)(E) - - - 35 8GP, 1 WD 2 2 1 2 1 1 - - - - - - Y - - BF506F (N/N)
BF518F SubSet
BF512 400 48 (16) 64 (32) 4 32 - Y(Y/Y) - - 40 8GP, 1 WD 2 2 1 2 1 0 - - - Y - - - - - BF518 (Y/N)
BF512F 400 48 (16) 64 (32) 4 32 1 (S) Y(Y/Y) - - 40 8GP, 1 WD 2 2 1 2 1 0 - - - Y - - - - - BF518 (Y/N)
BF514 400 48 (16) 64 (32) 4 32 - Y(Y/Y) - - 40 8GP, 1 WD 2 2 1 2 1 0 - - - Y - Y Y - - BF518 (Y/N)
BF514F 400 48 (16) 64 (32) 4 32 1 (S) Y(Y/Y) - - 40 8GP, 1 WD 2 2 1 2 1 0 - - - Y - Y Y - - BF518 (Y/N)
BF516 400 48 (16) 64 (32) 4 32 - Y(Y/Y) - - 40 8GP, 1 WD 2 2 1 2 1 0 1 - - Y - Y Y - - BF518 (Y/N)
BF516F 400 48 (16) 64 (32) 4 32 1 (S) Y(Y/Y) - - 40 8GP, 1 WD 2 2 1 2 1 0 1 - - Y - Y Y - - BF518 (Y/N)
BF518 400 48 (16) 64 (32) 4 32 - Y(Y/Y) - - 40 8GP, 1 WD 2 2 1 2 1 0 1 - - Y - Y Y - - BF518 (Y/N)
BF518F 400 48 (16) 64 (32) 4 32 1 (S) Y(Y/Y) - - 40 8GP, 1 WD 2 2 1 2 1 0 1 - - Y - Y Y - - BF518 (Y/N)
BF526 SubSet
BF522 400 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 - - - Y Y - - - - BF526 (Y/N)
BF524 400 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 - - Y(Y) Y Y - - - - BF526 (Y/N)
BF526 400 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 1 - Y(Y) Y Y - - - - BF526 (Y/N)
BF522C 400 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 - - - Y Y - - Y - BF526 (Y/N)
BF524C 400 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 - - Y(Y) Y Y - - Y - BF526 (Y/N)
BF526C 400 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 1 - Y(Y) Y Y - - Y - BF526 (Y/N)
BF527 SubSet
BF523 600 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 - - - Y Y - - - BF527 (N/N)
BF525 600 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 - - Y(Y) Y Y - - - - BF527 (N/N)
BF527 600 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 1 - Y(Y) Y Y - - - - BF527 (N/N)
BF523C 600 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 - - - Y Y - - Y - BF527 (N/N)
BF525C 600 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 - - Y(Y) Y Y - - Y - BF527 (N/N)
BF527C 600 64 (16) 64 (32) 4 32 - Y(Y/Y) - Y 48 8 GP, 1 WD 2 2 1 1 1 0 1 - Y(Y) Y Y - - Y - BF527 (N/N)
BF533 SubSet
BF531 400 32 (16) 16 (16) 4 1 - Y(Y/Y) - - 16 3 GP, 1 WD 1 2 1 1 0 0 - - - - - - - - - BF533 (N/N)
BF532 400 48 (16) 32 (32) 4 1 - Y(Y/Y) - - 16 3 GP, 1 WD 1 2 1 1 0 0 - - - - - - - - - BF533 (N/N)
BF533 600 80 (16) 64 (32) 4 1 - Y(Y/Y) - - 16 3 GP, 1 WD 1 2 1 1 0 0 - - - - - - - - - BF533 (N/N)
BF535 EOL - EOL
BF537 SubSet
BF534 500 64 (16) 64 (32) 4 2 - Y(Y/N) - - 48 8 GP, 1 WD 2 2 1 1 1 1 - - - - - - - - - BF537 (Y/N)
BF536 400 64 (16) 32 (32) 4 2 - Y(Y/N) - - 48 8 GP, 1 WD 2 2 1 1 1 1 1 - - - - - - - - BF537 (Y/N)
BF537 600 64 (16) 64 (32) 4 2 - Y(Y/N) - - 48 8 GP, 1 WD 2 2 1 1 1 1 1 - - - - - - - - BF537 (Y/N)
BF538F SubSet
BF538 533 80 (16) 64 (32) 4 - - Y(Y/N) - - 54 3 GP, 1 WD 3 4 1 3 2 1 - - - - - - - - - BF538F (N/N)
BF538F 533 80 (16) 64 (32) 4 - 2 (P)(E) Y(Y/N) - - 54 3 GP, 1 WD 3 4 1 3 2 1 - - - - - - - - - BF538F (N/N)
BF539 533 80 (16) 64 (32) 4 - - Y(Y/N) - - 54 3 GP, 1 WD 3 4 1 3 2 1 - - - - - - - - Y BF???? (N/N)
BF539F 533 80 (16) 64 (32) 4 - 2 (P)(E) Y(Y/N) - - 54 3 GP, 1 WD 3 4 1 3 2 1 - - - - - - - - Y BF???? (N/N)
BF548 SubSet
BF542 600 80 (16) 64 (32) 4 4 - - Y - 152 8 GP, 1 WD 3 3 1 2 1 1 - Y Y(Y) Y - Y Y - - BF548 (N/N)
BF544 533 80 (16) 64 (32) 4 64 4 - - Y - 152 11 GP, 1 WD 3 3 2 2 2 2 - - - Y Y - - - - BF548 (N/N)
BF547 600 80 (16) 64 (32) 4 128 4 - - Y - 152 8 GP, 1 WD 4 4 2 3 2 0 - Y Y(Y) Y Y Y Y - - BF548 (N/N)
BF548 533 80 (16) 64 (32) 4 128 4 - - Y - 152 8 GP, 1 WD 4 4 2 3 2 2 - Y Y(Y) Y Y Y Y - - BF548 (N/N)
BF549 533 80 (16) 64 (32) 4 128 4 - - Y - 152 8 GP, 1 WD 4 4 2 3 2 2 - Y Y(Y) Y Y Y Y - Y BF548 (N/N)
Dual Core BF561
BF561 600(2) - - 64 4 - Y(Y/N) - - 48 12 GP, 2 WD 1 2 2 1 0 0 0 - - - - - - - - BF561 (N/N)

In addition to the features in the table above, all Blackfin processors have the following peripherals
  • Debug/JTAG
    JTAG
    Joint Test Action Group is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.Today JTAG is also...

     Interface for in-system debugging
  • Real-time clock
  • Internal core voltage switching regulator
  • Watchdog timer
  • Timers/PWM outputs/PWM capture ports
  • Core timer (runs at core clock speed)

Core Features


What is regarded as the Blackfin "core" is contextually dependent.
  • For some applications, the DSP
    Digital signal processor
    A digital signal processor is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing.-Typical characteristics:...

     is central. It combines two 16-bit hardware MACs, two 40-bit ALU
    Arithmetic logic unit
    In computing, an arithmetic logic unit is a digital circuit that performs arithmetic and logical operations.The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers...

    s, and a 40-bit barrel shifter
    Barrel shifter
    A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers , and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift...

    . This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization
    Compiler optimization
    Compiler optimization is the process of tuning the output of a compiler to minimize or maximize some attributes of an executable computer program. The most common requirement is to minimize the time taken to execute a program; a less common one is to minimize the amount of memory occupied...

     performed by the compiler
    Compiler
    A compiler is a computer program that transforms source code written in a programming language into another computer language...

     and/or programmer
    Programmer
    A programmer, computer programmer or coder is someone who writes computer software. The term computer programmer can refer to a specialist in one area of computer programming or to a generalist who writes code for many kinds of software. One who practices or professes a formal approach to...

    .
  • Other applications emphasize the RISC core. It includes memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.


The ISA also features a high level of expressiveness, allowing the assembly programmer (or compiler) to highly optimize an algorithm to the hardware features present.

Memory and DMA


The Blackfin uses a byte-addressable, flat memory map. Internal L1 memory, internal L2 memory, external memory and all memory-mapped control registers reside in this 32-bit address space, so that from a programming point-of-view, the Blackfin has a Von Neumann architecture
Von Neumann architecture
The term Von Neumann architecture, aka the Von Neumann model, derives from a computer architecture proposal by the mathematician and early computer scientist John von Neumann and others, dated June 30, 1945, entitled First Draft of a Report on the EDVAC...

.

The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard Architecture
Harvard architecture
The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape and data in electro-mechanical counters...

. Instruction memory and data memory are independent and connect to the core via dedicated memory buses which allows for high sustained data rates between the core and L1 memory.

Portions of instruction and data L1 SRAM can be optionally configured as cache (independently).

Certain Blackfin processors also have between 64KB and 256KB of L2 memory. This memory runs slower than the core clock speed. Code and data can be mixed in L2.

Blackfin processors support a variety of external memories including SDRAM, DDR-SDRAM, NOR FLASH, NAND FLASH and SRAM. Some Blackfin also include mass-storage interfaces such as ATAPI, and SD/SDIO. They can support hundreds of megabytes of memory in the external memory space.

Coupled with the significant core and memory system is a DMA
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....

 engine that can operate between any of its peripheral
Peripheral
A peripheral is a device attached to a host computer, but not part of it, and is more or less dependent on the host. It expands the host's capabilities, but does not form part of the core computer architecture....

s and main (or external) memory. The processors typically have a dedicated DMA channel for each peripheral, which enables very high throughput
Throughput
In communication networks, such as Ethernet or packet radio, throughput or network throughput is the average rate of successful message delivery over a communication channel. This data may be delivered over a physical or logical link, or pass through a certain network node...

 for applications that can take advantage of it such as real-time standard-definition (D1) video encoding and decoding.

Microcontroller Features


The architecture contains the usual CPU, memory, and I/O found on microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...

s or microcontroller
Microcontroller
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM...

s. These features of enable operating systems.
  • Memory Protection Unit: All Blackfin processors contain a Memory Protection Unit(MPU). The MPU provides protection and caching strategies across the entire memory space. The MPU allows Blackfin to support many full-featured operating systems, RTOSs and kernels like ThreadX, µC/OS-II, or (noMMU) Linux. The Blackfin MPU does not provide address translation like a traditional Memory Management Unit
    Memory management unit
    A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...

     (MMU) thus it does not support virtual memory or separate memory addresses per process. This is why Blackfin currently can not support operating systems requiring virtual memory such as WinCE or QNX. Confusingly, in most of the Blackfin documentation, the MPU is referred to as a MMU.

  • User/Supervisor Modes: Blackfin supports three run-time modes: supervisor, user and emulation. In supervisor mode, all processor resources are accessible from the running process. However, when in user mode, system resources and regions of memory can be protected (with the help of the MPU). In a modern operating system or RTOS, the kernel typically runs in supervisor mode and threads/processes will run in user mode. If a thread crashes or attempts to access a protected resource (memory, peripheral, etc.) an exception will be thrown and the kernel will then be able to shut down the offending thread/process. The official guidance from ADI on how to use the Blackfin in non-OS environments is to reserve the lowest-priority interrupt for general-purpose code so that all software is run in supervisor space. This would not be as serious a deficiency if the Blackfin had more than 9 general-purpose interrupt vectors.

  • Variable-Length, RISC-Like Instruction Set: Blackfin supports 16, 32 and 64-bit instructions. Commonly-used control instructions are encoded as 16-bit opcodes while complex DSP and mathematically intensive functions are encoded as 32 and 64-bit opcodes. This variable length opcode encoding allows Blackfin to achieve good code density equivalent to modern microprocessor architectures.

Media Processing Features


The Blackfin instruction set contains media processing extensions to help accelerate pixel processing operations commonly used in video compression and image compression
Image compression
The objective of image compression is to reduce irrelevance and redundancy of the image data in order to be able to store or transmit data in an efficient form.- Lossy and lossless compression :...

 and decompression algorithms.

Peripherals


Blackfin processors contain a wide array of connectivity peripherals.
  • USB 2.0 OTG (On-The-Go)
    USB On-The-Go
    USB On-The-Go, often abbreviated USB OTG, is a specification that allows USB devices such as digital audio players or mobile phones to act as a host allowing a USB Flash Drive, mouse, or keyboard to be attached.- Architecture :...

  • ATAPI
  • MXVR : a MOST (Media Oriented Systems Transport) Network Interface Controller.
  • PPI (Parallel Peripheral Interface
    Parallel Peripheral Interface
    The Parallel Peripheral Interface is a peripheral found on the Blackfin embedded processor.The PPI is a half-duplex, bi-directional port that is designed to connect directly to LCDs, CMOS sensors, CCDs, video encoders , video decoders or any generic high speed, parallel device.The width of the...

    ) : A parallel input/output port that can be used to connect to LCDs, video encoders (video DACs), video decoders (video ADCs), CMOS sensors, CCDs and generic, parallel, high-speed devices. The PPI can run up to 75 MHz and can be configured from 8 to 16-bits wide.
  • SPORT : A synchronous, high speed serial port that can support TDM, I2S and a number of other configurable framing modes for connection to ADCs, DACs, other processors, FPGAs, etc.
  • CAN
    Controller Area Network
    Controller–area network is a vehicle bus standard designed to allow microcontrollers and devices to communicate with each other within a vehicle without a host computer....

     : A wide-area, low-speed serial bus that is fairly popular in automotive and industrial electronics.
  • UART (Universal Asynchronous Receiver Transmitter) : allows for bi-directional communication with RS232 devices (PCs, modems, PC peripherals, etc.), MIDI devices, IRDA
    IRDA
    IRDA may refer to:* Infrared Data Association, in information and communications technology , a standard for communication between devices over short distances using infrared signals...

     devices.
  • SPI : A fast serial bus used in many high-speed embedded electronics applications.
  • I²C
    I²C
    I²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...

     (also known as TWI (two-wire interface)) : A lower speed, shared serial bus.


Because all of the peripheral control registers are memory-mapped
Memory-mapped I/O
Memory-mapped I/O and port I/O are two complementary methods of performing input/output between the CPU and peripheral devices in a computer...

 in the normal address space, they are quite easy to set up.

Development Tools Hardware



Development Tools Software


ADI provides its own software development toolchain, CROSSCORE (VisualDSP++), but other options are also available, such as Green Hills Software
Green Hills Software
Green Hills Software is a privately owned company that builds operating systems and development tools for embedded systems. The company was founded in 1982 by Dan O'Dowd and Carl Rosenberg...

's MULTI IDE, the GNU GCC
GNU Compiler Collection
The GNU Compiler Collection is a compiler system produced by the GNU Project supporting various programming languages. GCC is a key component of the GNU toolchain...

 Toolchain for the Blackfin processor family, the OpenEmbedded
OpenEmbedded
OpenEmbedded is a software framework to create Linux distributions aimed for, but not restricted to, embedded devices. The build system is based on BitBake recipes, which behave similar to Gentoo's ebuilds....

 project, National Instruments' LabVIEW Embedded Module, or Microsoft Visual Studio through use of AxiomFount's AxiDotNet (integrated .NET Micro Framework
.NET Micro Framework
The .NET Micro Framework is an Open Source .NET platform for resource-constrained devices with at least 256 KBytes of flash and 64 KBytes of RAM. It includes a small version of the .NET CLR and supports development in C#, Visual Basic .NET, and debugging using Microsoft Visual Studio...

 based) solutions.

Supported Operating Systems, RTOSs & Kernels


Blackfin supports numerous commercial and open-source operating systems.
OS/RTOS/Kernels on Blackfin
Title Type!! Comments
Linux
Linux
Linux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...

 
Free Software GPL  Integrated into mainline kernel, distributed as part of the µClinux Distribution
ThreadX
ThreadX
ThreadX, developed and marketed by Express Logic, Inc. of San Diego, California, USA, is a real-time operating system . Similar RTOSes are available from other vendors such as VxWorks, Nucleus RTOS, OSE, QNX, LynxOS, etc...

 
Commercial
Nucleus
Nucleus RTOS
Nucleus OS is a real-time operating system and toolset created by the Embedded Systems Division of Mentor Graphics for various central processing unit platforms. Nucleus OS is an embedded software solution and is in an estimated 2.11 billion devices worldwide.Development is typically done on a...

 
Commercial
Fusion RTOS Commercial
µC/OS-II  Commercial/Source Available
velOSity Microkernel  Commercial
INTEGRITY
Integrity (operating system)
INTEGRITY is a real-time operating system produced and marketed by Green Hills Software. It is royalty-free, POSIX-certified, and intended for use in embedded systems needing reliability, availability, and fault tolerance. It is built atop the velOSity microkernel and is intended mainly for modern...

 
Commercial
RTEMS
RTEMS
RTEMS is a free open source real-time operating system designed for embedded systems....

 
Open-Source/GPL 
RTXC Quadros
RTXC Quadros
RTXC Quadros is a real time operating system written mainly in the C programming language. It is mainly intended for use in embedded systems.The RTXC RTOS was originally developed by AT Barrett and Associates in the 1970s. It is currently maintained by Quadros Systems, Inc...

 
Commercial/Source Available
T2 SDE  Open-Source/GPL 
VDK  Commercial ADI's real-time kernel. Ships with VisualDSP++.
TOPPERS/JSP Open-Source/GPL 
scmRTOS  Open-Source/MIT
MIT License
The MIT License is a free software license originating at the Massachusetts Institute of Technology . It is a permissive license, meaning that it permits reuse within proprietary software provided all copies of the licensed software include a copy of the MIT License terms...

 
Extremely small "Single-Chip Microcontroller Real-Time Operating System"
.NET Micro Framework
.NET Micro Framework
The .NET Micro Framework is an Open Source .NET platform for resource-constrained devices with at least 256 KBytes of flash and 64 KBytes of RAM. It includes a small version of the .NET CLR and supports development in C#, Visual Basic .NET, and debugging using Microsoft Visual Studio...

Open-Source Stand-alone version from Microsoft. Integrated version from AxiomFount.

External links