XCore XS1-L1
Encyclopedia
The XS1-L1
is a processor
designed by XMOS
. It is a 32-bit processor, that runs up to 8 concurrent threads. It was available as of June 2009 running at 400 MHz. As of April 2010 500 Mhz versions are available. Each thread can run at up to 125 MHz; four threads follow each other through the pipeline
, resulting in a top speed of 500 MIPS if at least four threads are active. The 500 MIPS of each core is equally distributed over all active threads. This allows the use of extra threads in order to hide latency.
, a virtual connection between two threads.
The XS1-L1 is an event driven processor
which enables the processor to stop a thread and restart it when an event is ready. In addition, a thread may be interrupted in order to deal with some external events.
The switch has eight external links, permitting a maximum throughput of 3.2 GBits/s to other cores.
The instruction set is a load-store instruction set.
All instructions execute in a single cycle. If an instruction does not need data from memory (for example, arithmetic operations), the instruction will prefetch a word of instructions.This acts like a very small instruction cache, but its behaviour can be predicted at compile time
, making timing behaviour as predictable as functional behaviour.
that enables the core to communicate with other cores. The switch has four internal links into the core, and eight external links, four of whom are available on I/O pins.
is a processor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
designed by XMOS
XMOS
XMOS is a fabless semiconductor company that develops multi-core multi-threaded processors designed to execute several real-time tasks, DSP, and control flow all at once.-Company history:...
. It is a 32-bit processor, that runs up to 8 concurrent threads. It was available as of June 2009 running at 400 MHz. As of April 2010 500 Mhz versions are available. Each thread can run at up to 125 MHz; four threads follow each other through the pipeline
Instruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
, resulting in a top speed of 500 MIPS if at least four threads are active. The 500 MIPS of each core is equally distributed over all active threads. This allows the use of extra threads in order to hide latency.
Description
The XS1-L1 comprises a single core processor and a switch. The execution core has a data path, a memory, and register banks for eight threads. The switches of two or more XS1-L1 processors can be connected using a link, whereupon threads can communicate with each other by exchanging messages through the switches. The switching mechanism is abstracted by means of a channelChannel (programming)
A Channel is a construct used in interprocess communication to represent some binding between concurrent processes. An object may be sent over a channel, and a process is able to receive any objects sent over a channel it has a reference to...
, a virtual connection between two threads.
The XS1-L1 is an event driven processor
Event (computing)
In computing an event is an action that is usually initiated outside the scope of a program and that is handled by a piece of code inside the program. Typically events are handled synchronous with the program flow, that is, the program has one or more dedicated places where events are handled...
which enables the processor to stop a thread and restart it when an event is ready. In addition, a thread may be interrupted in order to deal with some external events.
The switch has eight external links, permitting a maximum throughput of 3.2 GBits/s to other cores.
Instruction Set Architecture
Each thread has access to 12 general purpose registers, and a standard 3-operand instruction set is used for programming the thread. The instruction set is encoded densely, encoding most instructions in 16 bits, where 11 bits are used for specifying 3 operands, and 5 bits are used to encode the opcode. Less frequently used instructions are encoded in 32 bits.The instruction set is a load-store instruction set.
All instructions execute in a single cycle. If an instruction does not need data from memory (for example, arithmetic operations), the instruction will prefetch a word of instructions.This acts like a very small instruction cache, but its behaviour can be predicted at compile time
Compile time
In computer science, compile time refers to either the operations performed by a compiler , programming language requirements that must be met by source code for it to be successfully compiled , or properties of the program that can be reasoned about at compile time.The operations performed at...
, making timing behaviour as predictable as functional behaviour.
Concurrency
The core runs eight threads concurrently. These threads can communicate and synchronise using memory, registers, channels, locks, or synchronisers.- Each thread has single-cycle access to memory; and as such the single core can be viewed as an 8-processor SMPSymmetric multiprocessingIn computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...
.
- Threads can use locksSemaphore (programming)In computer science, a semaphore is a variable or abstract data type that provides a simple but useful abstraction for controlling access by multiple processes to a common resource in a parallel programming environment....
in order to guarantee mutual access. Access to locks is via single instructions.
- Threads can also use ChannelsChannel (programming)A Channel is a construct used in interprocess communication to represent some binding between concurrent processes. An object may be sent over a channel, and a process is able to receive any objects sent over a channel it has a reference to...
to communicate and synchronise allowing a CSPCommunicating sequential processesIn computer science, Communicating Sequential Processes is a formal language for describing patterns of interaction in concurrent systems. It is a member of the family of mathematical theories of concurrency known as process algebras, or process calculi...
style of programming. Channels can be operated on using single cycle instructions.
- Finally a BarrierBarrier (computer science)- Threads synchronization primitive :In parallel computing, a barrier is a type of synchronization method. A barrier for a group of threads or processes in the source code means any thread/process must stop at this point and cannot proceed until all other threads/processes reach this barrier.Many...
can be used; a barrier is entered using a single instruction, and when all threads that want to synchronise have reached the barrier they are all released within a single thread-cycle.
Switch
The XS1-L has a XSwitchXSwitch
The XSwitch is an interconnect used by the XCore processor. The interconnect protocol is defined by XMOS, and is based around routing messages comprising 9-bit tokens between cores on a network...
that enables the core to communicate with other cores. The switch has four internal links into the core, and eight external links, four of whom are available on I/O pins.