VerilogCSP
Encyclopedia
In integrated circuit design
, VerilogCSP is a set of macros added to Verilog HDL to support Communicating Sequential Processes
(CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits
.
VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies
, minimum cycle time, and slack.
Integrated circuit design
Integrated circuit design, or IC design, is a subset of electrical engineering and computer engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs...
, VerilogCSP is a set of macros added to Verilog HDL to support Communicating Sequential Processes
Communicating sequential processes
In computer science, Communicating Sequential Processes is a formal language for describing patterns of interaction in concurrent systems. It is a member of the family of mathematical theories of concurrency known as process algebras, or process calculi...
(CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits
Asynchronous circuit
An asynchronous circuit is a circuit in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer...
.
VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies
Latency (engineering)
Latency is a measure of time delay experienced in a system, the precise definition of which depends on the system and the time being measured. Latencies may have different meaning in different contexts.-Packet-switched networks:...
, minimum cycle time, and slack.