Registered memory
Encyclopedia
Registered memory modules
have a register
between the DRAM
modules and the system's memory controller
. They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise. Registered memory is often more expensive because of the lower volume and the additional components, so it is usually found only in applications where the need for scalability
and stability
outweighs the need for a low price (server
s, for example). Although most server-grade memory modules are both ECC and registered, there are both registered non-ECC modules and non-registered ECC modules.
Nominally, there is a performance penalty for using registered memory. Each read or write is buffered for one cycle between the memory bus and the DRAM, so the registered RAM can be thought of as running one clock cycle behind the equivalent unregistered DRAM. With SDRAM
, this only applies to the first cycle of a burst.
However, this performance penalty is not universal. There are other factors involved in memory access speed. For example, the Intel "Westmere" 5600 series of processors access memory using interleaving
, wherein memory access is distributed across 3 channels. If 2 memory DIMMs are used per channel, this "...results in a reduction of maximum memory bandwidth for 2DPC (DIMMs per channel) configurations with UDIMM
by some 5% in comparison to RDIMM." (p. 14). This is because "...when you go to 2 DIMMs per memory channel, due to the high electrical loading on the address and control lines, the memory controller use something called a “2T” or “2N” timing for UDIMMs. Consequently every command that normally takes a single clock cycle is stretched to two clock cycles to allow for settling time. Therefore, for two or more DIMMs per channel, RDIMMs will have lower latency and better bandwidth than UDIMMs."
However, some new large systems use "fully buffered memory". In normal registered/buffered memory, only the control lines are buffered whereas in fully buffered memory, the data lines are buffered as well.
Memory module
Memory module is a broad term used to refer to a series of dynamic random access memory integrated circuits modules mounted on a printed circuit board and designed for use in personal computers, workstations and servers....
have a register
Hardware register
In digital electronics, especially computing, a hardware register stores bits of information, in a way that all the bits can be written to or read out simultaneously.The hardware registers inside a central processing unit are called processor registers....
between the DRAM
Dynamic random access memory
Dynamic random-access memory is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1...
modules and the system's memory controller
Memory controller
The memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
. They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise. Registered memory is often more expensive because of the lower volume and the additional components, so it is usually found only in applications where the need for scalability
Scalability
In electronics scalability is the ability of a system, network, or process, to handle growing amount of work in a graceful manner or its ability to be enlarged to accommodate that growth...
and stability
Robustness (computer science)
In computer science, robustness is the ability of a computer system to cope with errors during execution or the ability of an algorithm to continue to operate despite abnormalities in input, calculations, etc. Formal techniques, such as fuzz testing, are essential to showing robustness since this...
outweighs the need for a low price (server
Server (computing)
In the context of client-server architecture, a server is a computer program running to serve the requests of other programs, the "clients". Thus, the "server" performs some computational task on behalf of "clients"...
s, for example). Although most server-grade memory modules are both ECC and registered, there are both registered non-ECC modules and non-registered ECC modules.
Nominally, there is a performance penalty for using registered memory. Each read or write is buffered for one cycle between the memory bus and the DRAM, so the registered RAM can be thought of as running one clock cycle behind the equivalent unregistered DRAM. With SDRAM
SDRAM
Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
, this only applies to the first cycle of a burst.
However, this performance penalty is not universal. There are other factors involved in memory access speed. For example, the Intel "Westmere" 5600 series of processors access memory using interleaving
Interleaved memory
Interleaved memory is a technique for compensating the relatively slow speed of DRAM. The CPU can access alternative sections immediately without waiting for memory to be cached. Multiple memory banks take turns supplying data....
, wherein memory access is distributed across 3 channels. If 2 memory DIMMs are used per channel, this "...results in a reduction of maximum memory bandwidth for 2DPC (DIMMs per channel) configurations with UDIMM
Unbuffered memory
Unbuffered memory is RAM where there is no hardware register between the memory controller and the RAM chips. Unbuffered memory is the opposite of registered memory. Registered memory is more stable, one clock cycle slower, and more expensive than unbuffered memory...
by some 5% in comparison to RDIMM." (p. 14). This is because "...when you go to 2 DIMMs per memory channel, due to the high electrical loading on the address and control lines, the memory controller use something called a “2T” or “2N” timing for UDIMMs. Consequently every command that normally takes a single clock cycle is stretched to two clock cycles to allow for settling time. Therefore, for two or more DIMMs per channel, RDIMMs will have lower latency and better bandwidth than UDIMMs."
Buffered memory
Buffered memory is an older term for registered memory (It's actually different and registered RAM won't fit in a standard slot, buffered refers to an electronic buffer placed between the memory and the memory controller).However, some new large systems use "fully buffered memory". In normal registered/buffered memory, only the control lines are buffered whereas in fully buffered memory, the data lines are buffered as well.