Nios II
Encyclopedia
Nios II is a 32-bit embedded-processor architecture designed specifically for the Altera
family of FPGAs. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from DSP
to system-control.
Nios II is comparable to MicroBlaze
, a competing softcore CPU for the Xilinx
family of FPGA. Unlike Microblaze, Nios II is licensable for standard-cell ASICs through a third-party IP provider, Synopsys
Designware. Through the Designware license, designers can port Nios-based designs from an FPGA-platform to a mass production ASIC-device.
Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios
.
architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by adding a predefined memory management unit, or defining custom instructions and custom peripherals.
source registers and optionally write back a result to a 32-bit destination register. By using custom instructions, the system designers can fine-tune the system hardware to meet performance goals and also the designer can easily handle the instruction as a macro in C
.
.
Development is hosted inside an Altera application called the Embedded Design Suite (EDS.) The EDS contains a complete integrated development environment to manage both hardware and software in two separate steps:
(GUI) allows users to choose the Nios-II's feature-set, and to add peripheral and I/O-blocks (timers, memory-controllers, serial interface, etc.) to the embedded system. When the hardware specification is complete, Quartus-II performs the synthesis, place & route to implement the entire system on the selected FPGA target.
IDE, the EDS includes a C/C++ compiler (based on the GNU toolchain
), debugger, and an instruction-set simulator. EDS allows programmers to test their application in simulation, or download and run their compiled application on the actual FPGA host.
Because the C/C++ development-chain is based on GCC, the vast majority of open source
software for Linux
compiles and runs with minimal or no modification. Third-party operating-systems have also been ported to Nios II. These include RTOS, Micrium MicroC/OS-II
, eCos
, μCLinux and FreeRTOS
.
Altera
Altera Corporation is a Silicon Valley manufacturer of PLDs . The company offered its first programmable logic device in 1984. PLDs can be reprogrammed during the design cycle as well as in the field to perform multiple functions, and they support a fairly fast design process...
family of FPGAs. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from DSP
Digital signal processing
Digital signal processing is concerned with the representation of discrete time signals by a sequence of numbers or symbols and the processing of these signals. Digital signal processing and analog signal processing are subfields of signal processing...
to system-control.
Nios II is comparable to MicroBlaze
MicroBlaze
The MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.-Overview:...
, a competing softcore CPU for the Xilinx
Xilinx
Xilinx, Inc. is a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model....
family of FPGA. Unlike Microblaze, Nios II is licensable for standard-cell ASICs through a third-party IP provider, Synopsys
Synopsys
Synopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
Designware. Through the Designware license, designers can port Nios-based designs from an FPGA-platform to a mass production ASIC-device.
Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios
Nios embedded processor
Nios was Altera's first configurable 16-bit embedded processor for its FPGA product-line. For new designs, Altera recommends the 32-bit Nios II. It is now considered obsolete.- See also :* LatticeMico8* LatticeMico32* MicroBlaze* PicoBlaze* Micon P200...
.
Key features
Like the original Nios, the Nios II architecture is a RISC soft-coreSoft microprocessor
A soft microprocessor is a microprocessor core that can be wholly implemented using logic synthesis...
architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by adding a predefined memory management unit, or defining custom instructions and custom peripherals.
Custom instructions
Similar to native Nios II instructions, user-defined instructions accept values from up to two 32-bitBit
A bit is the basic unit of information in computing and telecommunications; it is the amount of information stored by a digital device or other physical system that exists in one of two possible distinct states...
source registers and optionally write back a result to a 32-bit destination register. By using custom instructions, the system designers can fine-tune the system hardware to meet performance goals and also the designer can easily handle the instruction as a macro in C
C (programming language)
C is a general-purpose computer programming language developed between 1969 and 1973 by Dennis Ritchie at the Bell Telephone Laboratories for use with the Unix operating system....
.
Custom peripherals
For performance-critical systems that spend most CPU cycles executing a specific section of code, a user-defined peripheral can potentially offload part or all of the execution of a software-algorithm to user-defined hardware logic, improving power-efficiency or application throughput.Memory Management Unit
Introduced with Quartus 8.0, the optional MMU enables Nios II to run operating systems which require hardware-based paging and protection, such as the Linux kernel. Without an MMU, Nios is restricted to operating systems which use a simplified protection and virtual memory-model: e.g., µClinux and FreeRTOSFreeRTOS
FreeRTOS is a real-time operating system for embedded devices, being ported to several microcontrollers. It is distributed under the GPL with an optional exception...
.
Memory Protection Unit
Introduced with Quartus 8.0, the optional MPU provides memory protection similar to that provided by an MMU but with a simpler programming model and without the performance overhead associated with an MMU.Nios II CPU family
Nios II is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy).Nios II/f
The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include:- Separate instruction and data caches (512 BByteThe byte is a unit of digital information in computing and telecommunications that most commonly consists of eight bits. Historically, a byte was the number of bits used to encode a single character of text in a computer and for this reason it is the basic addressable element in many computer...
to 64 kBKilobyteThe kilobyte is a multiple of the unit byte for digital information. Although the prefix kilo- means 1000, the term kilobyte and symbol KB have historically been used to refer to either 1024 bytes or 1000 bytes, dependent upon context, in the fields of computer science and information...
) - Optional MMUMemory management unitA memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...
or MPU - Access to up to 2 GBGigabyteThe gigabyte is a multiple of the unit byte for digital information storage. The prefix giga means 109 in the International System of Units , therefore 1 gigabyte is...
of external address space - Optional tightly coupled memory for instructions and data
- Six-stage pipeline to achieve maximum DMIPS/MHz
- Single-cycle hardware multiply and barrel shifter
- Optional hardware divide option
- Dynamic branch prediction
- Up to 256 custom instructions and unlimited hardware accelerators
- JTAGJTAGJoint Test Action Group is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.Today JTAG is also...
debug module - Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace
Nios II/s
Nios II/s core is designed to maintain a balance between performance and cost. Features of Nios II/s include:- Instruction cache
- Up to 2 GB of external address space
- Optional tightly coupled memory for instructions
- Five-stage pipeline
- Static branch prediction
- Hardware multiply, divide, and shift options
- Up to 256 custom instructions
- JTAGJTAGJoint Test Action Group is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.Today JTAG is also...
debug module - Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace
Nios II/e
The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include:- Up to 2 GB of external address space
- JTAGJTAGJoint Test Action Group is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.Today JTAG is also...
debug module - Complete systems in fewer than 700 LEs
- Optional debug enhancements
- Up to 256 custom instructions
- Free, no license required
Avalon switch fabric interface
Nios II uses the Avalon switch fabric as the interface to its embedded peripherals. Compared to a traditional bus in a processor-based system, which lets only one bus master access the bus at a time, the Avalon switch fabric, using a slave-side arbitration scheme, lets multiple masters operate simultaneously.Development processes
Development for Nios II consists of two separate steps: hardware generation, and software creation.Development is hosted inside an Altera application called the Embedded Design Suite (EDS.) The EDS contains a complete integrated development environment to manage both hardware and software in two separate steps:
Hardware generation process
Nios II hardware designers use the SOPC (System-on-a-Programmable-Chip) Builder, a component of the Quartus-II package, to configure and generate a Nios system. The configuration graphical user interfaceGraphical user interface
In computing, a graphical user interface is a type of user interface that allows users to interact with electronic devices with images rather than text commands. GUIs can be used in computers, hand-held devices such as MP3 players, portable media players or gaming devices, household appliances and...
(GUI) allows users to choose the Nios-II's feature-set, and to add peripheral and I/O-blocks (timers, memory-controllers, serial interface, etc.) to the embedded system. When the hardware specification is complete, Quartus-II performs the synthesis, place & route to implement the entire system on the selected FPGA target.
Software creation process
A separate package, called the Embedded Design Suite (EDS), manages the software development. Based on the EclipseEclipse (software)
Eclipse is a multi-language software development environment comprising an integrated development environment and an extensible plug-in system...
IDE, the EDS includes a C/C++ compiler (based on the GNU toolchain
GNU toolchain
The GNU toolchain is a blanket term for a collection of programming tools produced by the GNU Project. These tools form a toolchain used for developing applications and operating systems....
), debugger, and an instruction-set simulator. EDS allows programmers to test their application in simulation, or download and run their compiled application on the actual FPGA host.
Because the C/C++ development-chain is based on GCC, the vast majority of open source
Open source
The term open source describes practices in production and development that promote access to the end product's source materials. Some consider open source a philosophy, others consider it a pragmatic methodology...
software for Linux
Linux
Linux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
compiles and runs with minimal or no modification. Third-party operating-systems have also been ported to Nios II. These include RTOS, Micrium MicroC/OS-II
MicroC/OS-II
MicroC/OS-II , is a low-cost priority-based pre-emptive real-time multitasking operating system kernel for microprocessors, written mainly in the C programming language...
, eCos
ECos
eCos is an open source, royalty-free, real-time operating system intended for embedded systems and applications which need only one process with multiple threads. It is designed to be customizable to precise application requirements of run-time performance and hardware needs...
, μCLinux and FreeRTOS
FreeRTOS
FreeRTOS is a real-time operating system for embedded devices, being ported to several microcontrollers. It is distributed under the GPL with an optional exception...
.
See also
- LatticeMico8
- LatticeMico32LatticeMico32LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays . It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.LatticeMico32...
- MicroBlazeMicroBlazeThe MicroBlaze is a soft processor core designed for Xilinx FPGAs from Xilinx. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.-Overview:...
- PicoBlazePicoblazePicoBlaze is the designation of a series of three free soft processor cores from Xilinx for use in their FPGA and CPLD products. They are based on a RISC architecture of 8 bits and can reach speeds up to 100 MIPS on the Virtex 4 FPGA's family. The processors have an 8-bit address and data port for...
- Micon P200
External links
- Altera's site about Nios II
- Nios users' community forum
- Nios community wiki
- RTEMSRTEMSRTEMS is a free open source real-time operating system designed for embedded systems....
real-time operating system - Cornell ECE576 Microcontroller course using NiosII
- FreeRTOS demo documentation for NiosII