NISC
Encyclopedia
No instruction set computing (NISC) is a computing architecture and compiler technology for designing highly efficient custom processors and hardware accelerators by allowing a compiler to have low-level control of hardware resources.
or microcode
. The compiler generates nanocodes which directly control functional units, registers and multiplexers of a given datapath. Giving low-level control to the compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology are:
Instruction-set and controller of processors are the most tedious and time-consuming parts to design. By eliminating these two, design of custom processing elements become significantly easier.
Furthermore, the datapath of NISC processors can even be generated automatically for a given application. Therefore, designers productivity is improved significantly.
Since NISC datapaths are very efficient and can be generated automatically, NISC technology is comparable to high level synthesis
(HLS) or C to HDL
synthesis approaches. In fact, one of the benefits of this architecture style is its capability to bridge these two technologies (custom processor design and HLS).
(CISC) to reduced instruction set computer
(RISC). In the early days of the computer industry, compiler technology did not exist and programming was done in assembly language
. To make programming easier, computer architects created complex instructions which were direct representations of high level functions of high level programming languages. Another force that encouraged instruction complexity was the lack of large memory blocks.
As compiler and memory technologies advanced, RISC architectures were introduced. RISC architectures need more instruction memory and require a compiler to translate high-level languages to RISC assembly code. Further advancement of compiler and memory technologies leads to emerging very long instruction word
(VLIW) processors, where the compiler controls the schedule of instructions and handles data hazards.
NISC is a successor of VLIW processors. In NISC, the compiler has both horizontal and vertical control of the operations in the datapath. Therefore, the hardware is much simpler. However the control memory size is larger than the previous generations. To address this issue, low-overhead compression techniques can be used.
Overview
NISC is a statically-scheduled horizontal nanocoded architecture (SSHNA). The term "statically scheduled" means that the operation scheduling and hazard handling are done by a compiler. The term "horizontal nanocoded" means that NISC does not have any predefined instruction setInstruction set
An instruction set, or instruction set architecture , is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O...
or microcode
Microcode
Microcode is a layer of hardware-level instructions and/or data structures involved in the implementation of higher level machine code instructions in many computers and other processors; it resides in special high-speed memory and translates machine instructions into sequences of detailed...
. The compiler generates nanocodes which directly control functional units, registers and multiplexers of a given datapath. Giving low-level control to the compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology are:
- Simpler controller: no hardware scheduler, no instruction decoder
- Better performance: more flexible architecture, better resource utilization
- Easier to design: no need for designing instruction-sets
Instruction-set and controller of processors are the most tedious and time-consuming parts to design. By eliminating these two, design of custom processing elements become significantly easier.
Furthermore, the datapath of NISC processors can even be generated automatically for a given application. Therefore, designers productivity is improved significantly.
Since NISC datapaths are very efficient and can be generated automatically, NISC technology is comparable to high level synthesis
High-level synthesis
High-level synthesis , sometimes referred to as C synthesis, electronic system level synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates hardware that implements that behavior. The...
(HLS) or C to HDL
C to HDL
C to HDL tools convert C or C-like computer program code into a hardware description language such as VHDL or Verilog. The converted code can then be synthesized and translated into a hardware device such as a field-programmable gate array...
synthesis approaches. In fact, one of the benefits of this architecture style is its capability to bridge these two technologies (custom processor design and HLS).
History
In the past, microprocessor design technology evolved from complex instruction set computerComplex instruction set computer
A complex instruction set computer , is a computer where single instructions can execute several low-level operations and/or are capable of multi-step operations or addressing modes within single instructions...
(CISC) to reduced instruction set computer
Reduced instruction set computer
Reduced instruction set computing, or RISC , is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer...
(RISC). In the early days of the computer industry, compiler technology did not exist and programming was done in assembly language
Assembly language
An assembly language is a low-level programming language for computers, microprocessors, microcontrollers, and other programmable devices. It implements a symbolic representation of the machine codes and other constants needed to program a given CPU architecture...
. To make programming easier, computer architects created complex instructions which were direct representations of high level functions of high level programming languages. Another force that encouraged instruction complexity was the lack of large memory blocks.
As compiler and memory technologies advanced, RISC architectures were introduced. RISC architectures need more instruction memory and require a compiler to translate high-level languages to RISC assembly code. Further advancement of compiler and memory technologies leads to emerging very long instruction word
Very long instruction word
Very long instruction word or VLIW refers to a CPU architecture designed to take advantage of instruction level parallelism . A processor that executes every instruction one after the other may use processor resources inefficiently, potentially leading to poor performance...
(VLIW) processors, where the compiler controls the schedule of instructions and handles data hazards.
NISC is a successor of VLIW processors. In NISC, the compiler has both horizontal and vertical control of the operations in the datapath. Therefore, the hardware is much simpler. However the control memory size is larger than the previous generations. To address this issue, low-overhead compression techniques can be used.
See also
- Complex instruction set computerComplex instruction set computerA complex instruction set computer , is a computer where single instructions can execute several low-level operations and/or are capable of multi-step operations or addressing modes within single instructions...
(CISC) - Reduced instruction set computerReduced instruction set computerReduced instruction set computing, or RISC , is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer...
(RISC) - Minimal instruction set computerMinimal instruction set computerMinimal Instruction Set Computer is a processor architecture with a very small number of basic operations and corresponding opcodes. Such instruction sets are commonly stack based rather than register based to reduce the size of operand specifiers. Such a stack machine architecture is inherently...
(MISC) - One instruction set computerOne instruction set computerA one instruction set computer , sometimes called an ultimate reduced instruction set computer , is an abstract machine that uses only one instruction – obviating the need for a machine language opcode...
(OISC) - Zero instruction set computerZero Instruction Set ComputerIn computer science, ZISC stands for Zero Instruction Set Computer, which refers to a chip technology based on pure pattern matching and absence of instructions in the classical sense...
(ZISC) - C to HDLC to HDLC to HDL tools convert C or C-like computer program code into a hardware description language such as VHDL or Verilog. The converted code can then be synthesized and translated into a hardware device such as a field-programmable gate array...
Further reading
- Chapter 2.