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An inter-processor interrupt (IPI) is a special type of interrupt
Interrupt

In computing, an interrupt is an asynchronous communication signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
 by which one processor may interrupt another processor in a multiprocessor system. IPIs are typically used to implement a cache coherency
Cache coherency

In computing, cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence....
 synchronization
Synchronization

Synchronization or synchronisation is timekeeping which requires the coordination of events to operate a system in unison. The familiar Conducting of an orchestra serves to keep the orchestra in time....
 point.

In a Windows based multiprocessor system, a processor may interrupt another processor for the following reasons:

1. Queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution.
2.






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An inter-processor interrupt (IPI) is a special type of interrupt
Interrupt

In computing, an interrupt is an asynchronous communication signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
 by which one processor may interrupt another processor in a multiprocessor system. IPIs are typically used to implement a cache coherency
Cache coherency

In computing, cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence....
 synchronization
Synchronization

Synchronization or synchronisation is timekeeping which requires the coordination of events to operate a system in unison. The familiar Conducting of an orchestra serves to keep the orchestra in time....
 point.

In a Windows based multiprocessor system, a processor may interrupt another processor for the following reasons:

1. Queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution.
2. Updating the processor's translation look-aside buffers cache.
3. System Shutdown.
4. System Crash.

In windows, this has IRQL as 29.

In x86
X86 architecture

The generic term x86 refers to the most commercially successful instruction set architecture in the history of personal computing. It derived from the model numbers, ending in "86", of the first few processor generations Backward compatibility with the original Intel 8086....
 based systems, an IPI synchronizes the cache and Memory Management Unit
Memory management unit

A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to computer memory requested by the central processing unit ....
 (MMU) between processors.

See also

  • Advanced Programmable Interrupt Controller
    Advanced Programmable Interrupt Controller

    An Advanced Programmable Interrupt Controller is a more intricate Programmable Interrupt Controller containing a magnitude more outputs, much more complex priority schema, and Advanced IRQ management....
  • Interrupt
    Interrupt

    In computing, an interrupt is an asynchronous communication signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
  • Interrupt Handler
    Interrupt handler

    An interrupt handler, also known as an interrupt service routine , is a callback subroutine in an operating system or device driver whose execution is triggered by the reception of an interrupt....
  • Non-Maskable Interrupt
    Non-Maskable interrupt

    A non-maskable interrupt is a computer Central processing unit interrupt that cannot be ignored by standard interrupt masking techniques in the system....
  • Programmable Interrupt Controller
    Programmable Interrupt Controller

    A programmable interrupt controller is a device which allows priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in the order of their relative priority....