Four-phase logic
Encyclopedia
Four-phase logic is a type of, and design methodology for, dynamic logic
; it enabled non-specialist engineers to design quite complex ICs
, using either PMOS
or NMOS
processes.
, invented four-phase logic, and communicated the idea to Frank Wanlass
at Fairchild Semiconductor
; Wanlass promoted this logic form at General Instruments Microelectronics Division.
Booher made the first working four-phase chip, the Autonetics DDA Integrator, during February 1966; he later designed several chips for and built the Autonetics D200 airborne computer using this technique.
In April 1967, Joel Karp and Elizabeth de Atley published an article "Use four-phase MOS IC logic" in Electronic Design magazine.
In the same year, Cohen, Rubenstein, and Wanlass published "MTOS four phase clock systems."
Wanlass had been director of research and engineering at General Instruments Microelectronics Division in New York since leaving Fairchild Semiconductor
in 1964.
Lee Boysel
, a disciple of Wanlass
and a designer at Fairchild Semiconductor
, and later founder of Four-Phase Systems, gave a "late news" talk on a four-phase 8-bit adder device in October 1967 at the International Electron Devices meeting.
J. L. Seely, manager of MOS Operations at General Instruments Microelectronics Division, also wrote about four-phase logic in late 1967.
In 1968 Boysel published an article "Adder On a Chip: LSI Helps Reduce Cost of Small Machine" in Electronics magazine;
Four-phase papers from Y. T. Yen also appear that year.
Other papers followed shortly.
Boysel recalls that four-phase dynamic logic allowed him to achieve 10X the packing density, 10X the speed, and 1/10 the power, compared to other MOS techniques being used at the time (metal-gate
saturated-load PMOS logic
), using the first-generation MOS process at Fairchild.
The ø1 and ø3 clocks need to be non-overlapping, as do the ø2 and ø4 clocks. Considering the 1 gate, during the ø1 clock high time (also known as the precharge time) the output C precharges up to V(ø1)-Vth, where Vth represents the threshold of the precharge transistor. During the next quarter clock cycle (the sample time), when ø1 is low and ø2 is high, C either stays high (if A or B are low) or C gets discharged low (if A and B are high).
The A and B inputs must be stable throughout this sample time. The output C becomes valid during this time - and therefore a 1 gate output can't drive another 1 gate's inputs. Hence 1 gates have to feed 3 gates and they in turn have to feed 1 gates.
One more thing is useful - 2 and 4 gates. A 2 gate precharges on ø1 and samples on ø3:
and a 4 gate precharges on ø3 and samples on ø1.
Gate interconnection rules are: 1 gates can drive 2 gates and/or 3 gates; 2 gates can drive only 3 gates, 3 gates can drive 4 gates and/or 1 gates, 4 gates can drive only 1 gates:
gate includes a register. It's worth noting that the layout does not require the bussing of any power supplies - only clock lines are bussed. Also, since the design technique is ratioless (cf. static logic), many designs can use minimum-size transistors.
There are some difficulties:
, the precharge transistor could be changed to be the complement of the logic transistor type, which allows the gate's output to charge quickly all the way up to the high level of the clock line, thus improving the speed, signal swing, power consumption, and noise margin. This technique is used in domino logic
.
Dynamic logic
Dynamic logic may mean:* In theoretical computer science, dynamic logic is a modal logic for reasoning about dynamic behaviour* In digital electronics, dynamic logic is a technique used for combinatorial circuit design* A different concept proposed by Leonid Perlovsky...
; it enabled non-specialist engineers to design quite complex ICs
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
, using either PMOS
PMOS logic
P-type metal-oxide-semiconductor logic uses p-type metal-oxide-semiconductor field effect transistors to implement logic gates and other digital circuits...
or NMOS
NMOS logic
N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field effect transistors to implement logic gates and other digital circuits...
processes.
History
R. K. "Bob" Booher, an engineer at AutoneticsAutonetics
Autonetics was a division of North American Aviation. Through a series of mergers, Autonetics is now part of Boeing.- General Background of the Anaheim Facility :...
, invented four-phase logic, and communicated the idea to Frank Wanlass
Frank Wanlass
Frank Marion Wanlass was an electrical engineer. He obtained his PhD from the University of Utah. He invented CMOS logic circuits in 1963 while working at Fairchild Semiconductor. He was given U.S. patent #3,356,858 for "Low Stand-By Power Complementary Field Effect Circuitry" in 1967...
at Fairchild Semiconductor
Fairchild Semiconductor
Fairchild Semiconductor International, Inc. is an American semiconductor company based in San Jose, California. Founded in 1957, it was a pioneer in transistor and integrated circuit manufacturing...
; Wanlass promoted this logic form at General Instruments Microelectronics Division.
Booher made the first working four-phase chip, the Autonetics DDA Integrator, during February 1966; he later designed several chips for and built the Autonetics D200 airborne computer using this technique.
In April 1967, Joel Karp and Elizabeth de Atley published an article "Use four-phase MOS IC logic" in Electronic Design magazine.
In the same year, Cohen, Rubenstein, and Wanlass published "MTOS four phase clock systems."
Wanlass had been director of research and engineering at General Instruments Microelectronics Division in New York since leaving Fairchild Semiconductor
Fairchild Semiconductor
Fairchild Semiconductor International, Inc. is an American semiconductor company based in San Jose, California. Founded in 1957, it was a pioneer in transistor and integrated circuit manufacturing...
in 1964.
Lee Boysel
Lee Boysel
Lee Boysel is an American engineer, and entrepreneur. While at Fairchild Semiconductor, he developed four-phase logic and built the first integrated circuit with over 100 logic gates. He founded Four-Phase Systems to commercialize the technology, and sold the company to Motorola in...
, a disciple of Wanlass
and a designer at Fairchild Semiconductor
Fairchild Semiconductor
Fairchild Semiconductor International, Inc. is an American semiconductor company based in San Jose, California. Founded in 1957, it was a pioneer in transistor and integrated circuit manufacturing...
, and later founder of Four-Phase Systems, gave a "late news" talk on a four-phase 8-bit adder device in October 1967 at the International Electron Devices meeting.
J. L. Seely, manager of MOS Operations at General Instruments Microelectronics Division, also wrote about four-phase logic in late 1967.
In 1968 Boysel published an article "Adder On a Chip: LSI Helps Reduce Cost of Small Machine" in Electronics magazine;
Four-phase papers from Y. T. Yen also appear that year.
Other papers followed shortly.
Boysel recalls that four-phase dynamic logic allowed him to achieve 10X the packing density, 10X the speed, and 1/10 the power, compared to other MOS techniques being used at the time (metal-gate
Metal gate
A metal gate, in the context of a lateral Metal-Oxide-Semiconductor MOS stack, is just that—the gate material is made from a metal.For decades, the industry had moved away from metal as the gate material in the MOS stack due to fabrication complications...
saturated-load PMOS logic
PMOS logic
P-type metal-oxide-semiconductor logic uses p-type metal-oxide-semiconductor field effect transistors to implement logic gates and other digital circuits...
), using the first-generation MOS process at Fairchild.
Structure
There are basically two types of logic gate - a '1' gate and a '3' gate. These differ only in the clock phases used to drive them. A gate can have any logic function; thus potentially each and every gate has a customized layout. An example 2-input NAND 1 gate and an inverter 3 gate, together with their clock phases (the example uses NMOS transistors), are shown below:The ø1 and ø3 clocks need to be non-overlapping, as do the ø2 and ø4 clocks. Considering the 1 gate, during the ø1 clock high time (also known as the precharge time) the output C precharges up to V(ø1)-Vth, where Vth represents the threshold of the precharge transistor. During the next quarter clock cycle (the sample time), when ø1 is low and ø2 is high, C either stays high (if A or B are low) or C gets discharged low (if A and B are high).
The A and B inputs must be stable throughout this sample time. The output C becomes valid during this time - and therefore a 1 gate output can't drive another 1 gate's inputs. Hence 1 gates have to feed 3 gates and they in turn have to feed 1 gates.
One more thing is useful - 2 and 4 gates. A 2 gate precharges on ø1 and samples on ø3:
and a 4 gate precharges on ø3 and samples on ø1.
Gate interconnection rules are: 1 gates can drive 2 gates and/or 3 gates; 2 gates can drive only 3 gates, 3 gates can drive 4 gates and/or 1 gates, 4 gates can drive only 1 gates:
Usage
Four-phase logic works well; in particular there are no race hazards because every combinational logicCombinational logic
In digital circuit theory, combinational logic is a type of digital logic which is implemented by boolean circuits, where the output is a pure function of the present input only. This is in contrast to sequential logic, in which the output depends not only on the present input but also on the...
gate includes a register. It's worth noting that the layout does not require the bussing of any power supplies - only clock lines are bussed. Also, since the design technique is ratioless (cf. static logic), many designs can use minimum-size transistors.
There are some difficulties:
- The gate output is dynamic. This means that its state is held on capacitance at the gate output. But the output track can cross clock lines and other gate outputs, all of which can change the charge on the capacitor. In order that the gate output voltage remains at some safe 0 or 1 level during the cycle the amount of change has to be calculated and, if necessary, additional (diffusion) capacitance has to be added to the output node.
- For a given supply voltage, process, and clock frequency, the designer has to do some calculations so that the layout engineers can, in turn, do their calculations to work out the 'bulk-up' capacitance needed for each gate. A gate with a lot of capacitance load could need bigger than minimum input transistors (in order that the load could be discharged in time). This in turn increases the load on the gates driving that gate's inputs. So it can happen, especially in high-frequency designs, that the gate sizing keeps on increasing if the speed target is too aggressive.
Evolution
With the advent of CMOSCMOS
Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...
, the precharge transistor could be changed to be the complement of the logic transistor type, which allows the gate's output to charge quickly all the way up to the high level of the clock line, thus improving the speed, signal swing, power consumption, and noise margin. This technique is used in domino logic
Domino logic
Domino logic is a CMOS-based evolution of the dynamic logic techniques which were based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing. It was developed to speed up circuits....
.