ERM (e Reuse Methodology)
Encyclopedia
The e Reuse Methodology was the first reuse methodology to emerge in the Hardware Verification Language space and was used in conjunction with the e Hardware Verification Language
. It was invented in 2001 by Verisity Design and was released in 2002. The methodology was composed of methodology guidelines for such topics as:
The e Reuse Methodology was widely accepted by verification engineers and, to this day, is the most widely used and successful reuse methodology with thousands of successful projects.
eRM formed the basis of the URM (Universal Reuse Methodolgy) developed by Cadence Design Systems for the SystemVerilog Language. URM, together with contribution from Mentor Graphics' AVM, later went on to become the OVM (Open Verification Methology
) and, finally the UVM (Universal Verification Methodology)
today.
E (verification language)
e is a hardware verification language which is tailored to implementing highly flexible and reusable verification testbenches.- History :...
. It was invented in 2001 by Verisity Design and was released in 2002. The methodology was composed of methodology guidelines for such topics as:
- File naming conventions
- Functional partitioning of the testbench
- Code packaging Guidelines
- Sequence and message class libraries
The e Reuse Methodology was widely accepted by verification engineers and, to this day, is the most widely used and successful reuse methodology with thousands of successful projects.
eRM formed the basis of the URM (Universal Reuse Methodolgy) developed by Cadence Design Systems for the SystemVerilog Language. URM, together with contribution from Mentor Graphics' AVM, later went on to become the OVM (Open Verification Methology
Open Verification Methodology
The Open Verification Methodology is a documented methodology with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008, and regular updates have expanded its functionality. The latest version is OVM...
) and, finally the UVM (Universal Verification Methodology)
Universal Verification Methodology
The Universal Verification Methodology is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM which was, to a large part, based on the eRM for the e Verification Language developed by Verisity Design in 2001...
today.