AMD Horus
Encyclopedia
The Horus system, designed by Newisys
for AMD, was created to enable AMD Opteron
machines to extend beyond the current limit of 8-way (CPU
sockets) architectures. The Opteron CPUs feature a cache-coherent HyperTransport
(ccHT) bus to permit glueless, multiprocessor interconnect between physical CPU packages but as there is a maximum of three ccHT interfaces per chip, the systems are limited to a maximum of 8 sockets. The HyperTransport bus is also distance restricted and does not permit off-system interconnect.
The Horus system overcomes these limitations by creating a pseudo-Opteron, the Horus chip, which connects to four real Opterons via the HyperTransport bus. As far as the Opterons are concerned they are in a five-way system and this is the basic Horus node (as called 'quad'). The Horus chip then provides an additional off-board interface (based around the InfiniBand
standards) which can link to additional Horus nodes (up to 8). The chip handles the necessary translation between local and off-board ccHT communications. By putting the CPUs around the Horus chip with 12-bit lanes running at 3125 MHz with InfiniBand technology (8b/10b encoding
), this system has an effective internal speed of 30 Gbit/s.
With 8 'quads' connected together, each with the maximum of four Opteron sockets per node, the Horus system allows a total of 32 CPU sockets in a single machine. Dual and future quad-core chips will also be supported, allowing a single system to scale to over a hundred processing cores.
Newisys
Newisys, a Server and Storage company with expertise in glue-chips for Opterons, based in Austin, Texas, was co-founded by Claymon A Cipione and Phil Hester in 2000, and was acquired in 2004 by manufacturer Sanmina-SCI...
for AMD, was created to enable AMD Opteron
Opteron
Opteron is AMD's x86 server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture . It was released on April 22, 2003 with the SledgeHammer core and was intended to compete in the server and workstation markets, particularly in the same...
machines to extend beyond the current limit of 8-way (CPU
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
sockets) architectures. The Opteron CPUs feature a cache-coherent HyperTransport
HyperTransport
HyperTransport , formerly known as Lightning Data Transport , is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2, 2001...
(ccHT) bus to permit glueless, multiprocessor interconnect between physical CPU packages but as there is a maximum of three ccHT interfaces per chip, the systems are limited to a maximum of 8 sockets. The HyperTransport bus is also distance restricted and does not permit off-system interconnect.
The Horus system overcomes these limitations by creating a pseudo-Opteron, the Horus chip, which connects to four real Opterons via the HyperTransport bus. As far as the Opterons are concerned they are in a five-way system and this is the basic Horus node (as called 'quad'). The Horus chip then provides an additional off-board interface (based around the InfiniBand
InfiniBand
InfiniBand is a switched fabric communications link used in high-performance computing and enterprise data centers. Its features include high throughput, low latency, quality of service and failover, and it is designed to be scalable...
standards) which can link to additional Horus nodes (up to 8). The chip handles the necessary translation between local and off-board ccHT communications. By putting the CPUs around the Horus chip with 12-bit lanes running at 3125 MHz with InfiniBand technology (8b/10b encoding
8B/10B encoding
In telecommunications, 8b/10b is a line code that maps 8-bit symbols to 10-bit symbols to achieve DC-balance and bounded disparity, and yet provide enough state changes to allow reasonable clock recovery. This means that the difference between the count of 1s and 0s in a string of at least 20 bits...
), this system has an effective internal speed of 30 Gbit/s.
With 8 'quads' connected together, each with the maximum of four Opteron sockets per node, the Horus system allows a total of 32 CPU sockets in a single machine. Dual and future quad-core chips will also be supported, allowing a single system to scale to over a hundred processing cores.