TI MSP430
Encyclopedia
The MSP430 is a mixed-signal
microcontroller
family from Texas Instruments
. Built around a 16-bit
CPU, the MSP430 is designed for low cost, and specifically, low power consumption embedded applications. The architecture dates from the 1990s and is reminiscent of the DEC PDP-11
.
drawn in idle mode can be less than 1 microamp. The top CPU speed is 25 MHz. It can be throttled back for lower power consumption. The MSP430 also utilizes six different Low-Power Modes, which can disable unneeded clocks and CPU. This allows the MSP430 to sleep, while its peripheral
s continue to work without the need for an energy hungry processor
. Additionally, the MSP430 is capable of wake-up times below 1 microsecond, allowing the microcontroller to stay in sleep mode longer, minimizing its average current consumption. Note that MHz is not equivalent to Million instructions per second (MIPS), and different architectures can obtain different MIPS rates at lower CPU clock frequencies, which can result in lower dynamic power consumption for an equivalent amount of digital processing.
The device comes in a variety of configurations featuring the usual peripherals: internal oscillator, timer
including PWM
, watchdog
, USART, SPI
, I2C, 10/12/14/16-bit ADC
s, and brownout
reset circuitry. Some less usual peripheral options include comparator
s (that can be used with the timers to do simple ADC), on-chip op-amp
s for signal conditioning
, 12-bit DAC
, LCD
driver, hardware multiplier, USB, and DMA
for ADC results. Apart from some older EPROM
(PMS430E3xx) and high volume mask ROM
(MSP430Cxxx) versions, all of the devices are in-system programmable
via JTAG
(full four-wire or Spy-Bi-Wire
) or a built in bootstrap loader (BSL) using RS-232
.
There are, however, limitations that preclude its use in more complex embedded systems. The MSP430 does not have an external memory bus
, so is limited to on-chip memory (up to 256 KB Flash memory
and 16 KB RAM
) which might be too small for applications that require large buffers or data tables. Also, although it has a very capable DMA controller, it is very difficult to use it to move data off the chip due to a lack of a DMA output strobe.
Trailing suffix letters indicate options not visible to software:
.
The 3xx and 1xx generations were limited to a 16 bit address space. In the later generations this was expanded to include '430X' instructions that allow a 20 bit address space. As happened with the PDP-11, and as one might expect, extending the addressing range beyond the 16 bit word size introduced some peculiarities and inefficiencies for programs larger than 64 kBytes.
In the following list, it helps to think of the typical 200 mA·Hr capacity of a CR2032 lithium coin cell as 200,000 μA·Hr, or 22.8 μA·year. Thus, considering only the CPU draw, such a battery could supply a 0.7 μA current draw for 32 years. (In reality, battery self-discharge
would reduce this number.)
The significance of the 'RAM retention' vs the 'real-time clock mode' is that in real time clock mode the CPU can go to sleep with a clock running which will wake it up at a specific future time. In RAM retention mode, some external signal is required to wake it, e.g. I/O pin signal or SPI slave receive interrupt.
oscillator that can automatically synchronize to a low-speed (32 kHz) crystal. This generation does not support EEPROM
memory, only mask ROM and UV-eraseable and one-time programmable EPROM
. Later generations provide only flash ROM and mask ROM
options. These devices offer 2.5–5.5 V operation, up to 32 KB ROM.
Note that when the flash size is over 64K words (128 KBytes), instruction addresses can no longer be encoded in just two bytes. This change in pointer size causes some incompatibilities with previous parts.
, with a single address space for instructions and data. Memory is byte
-addressed, and pairs of bytes are combined little-endian to make 16-bit words.
The processor contains 16 16-bit registers, of which 4 are dedicated to special purposes: R0 is the program counter
, R1 is the stack pointer, R2 is the status register
, and R3 is a special register called the constant generator, providing access to 6 commonly used constant values without requiring an additional operand. R3 always reads as 0 and writes to it are ignored. R4 through R15 are available for general use.
The instruction set is very simple; there are 27 instructions in three families. Most instructions are available in .B (8-bit byte) and .W (16-bit word) suffixed versions, depending on the value of a B/W bit: the bit is set to 1 for 8-bit and 0 for 16-bit. A missing suffix is equivalent to .W. Byte operations to memory affect only the addressed byte, while byte operations to registers clear the most significant byte.
Instructions are 16 bits, followed by up to two 16-bit extension words. Addressing modes are specified by the 2-bit As field and the 1-bit Ad field. Some special versions can be constructed using R0, and modes other than register direct using R2 (the status register) and R3 (the constant generator) are interpreted specially. Ad can use only a subset of the addressing modes for As.
Indexed addressing modes add a 16-bit extension word to the instruction. If both source and destination are indexed, the source extension word comes first. x refers to the next extension word in the instruction stream in the table below.
Instructions generally take 1 cycle per word fetched or stored, so instruction times range from 1 cycle for a simple register-register instruction to 6 cycles for an instruction with both source and destination indexed.
The MSP430X extension with 20-bit addressing adds additional instructions that can require up to 10 clock cycles. Setting or clearing a peripheral bit takes two clocks. A jump, taken or not takes two clocks. With the 2xx series 2 MCLKs is 125 ns at 16 MHz.
Moves to the program counter are allowed and perform jumps. Return from subroutine, for example, is implemented as MOV @SP+,PC.
When R0 (PC) or R1 (SP) are used with the autoincrement addressing mode, they are always incremented by two. Other registers (R4 through R15) are incremented by the operand size, either 1 or 2 bytes.
The status register contains 4 arithmetic status bits, a global interrupt enable, and 4 bits that disable various clocks to enter low-power mode. When handling an interrupt, the processor saves the status register on the stack and clears the low-power bits. If the interrupt handler does not modify the saved status register, returning from the interrupt will then resume the original low-power mode.
Note that the immediate constants −1 (0xffff), 0, 1, 2, 4 and 8 can be specified in a single-word instruction without needing a separate immediate operand.
The extended instructions include some additional capabilities, notably multi-bit shifts and multi-register load/store operations.
20-bit operations use the length suffix ".A" (for address) instead of .B or .W. .W is still the default. In general, shorter operations clear the high-order bits of the destination register.
The new instructions are as follows:
All other instructions can have a prefix word added which extends them to 20 bits. The prefix word contains an additional operand size bit, which is combined with the existing B/W bit to specify the operand size. There is one unused size combination; there are indications that this might be used in future for a 32-bit operand size.
The prefix word comes in two formats, and the choice between them depends on the instruction which follows.
If the instruction has any non-register operands, then the simple form is used, which provides 2 4-bit fields to extend any offset or immediate constant in the instruction stream.
If the instruction is register-to-register, a different extension word is used. This includes a "ZC" flag which suppresses carry-in (useful for instructions like DADD which always use the carry bit), and a repeat count. A 4-bit field in the extension word encodes either a repeat count (0–15 repetitions in addition to the initial execution), or a register number which contains a 4-bit repeat count.
0x0000–0x0007 : Processor special function registers (interrupt control registers)
0x0008–0x00FF : 8-bit peripherals. These must be accessed using 8-bit loads and stores.
0x0100–0x01FF : 16-bit peripherals. These must be accessed using 16-bit loads and stores.
0x0200–0x09FF : Up to 2048 bytes of RAM
.
0x0C00–0x0FFF : 1024 bytes of bootstrap loader ROM (flash ROM parts only).
0x1000–0x10FF : 256 bytes of data flash ROM (flash ROM parts only).
0x1100–0x38FF : Extended RAM on models with more than 2048 bytes of RAM. (0x1100–0x18FF is a copy of 0x0200–0x09FF)
0x1100–0xFFFF : Up to 60 kilobyte
s of program ROM. Smaller ROMs start at higher addresses. The last 16 or 32 bytes are interrupt vector
s.
A few models include more than 2048 bytes of RAM; in that case RAM begins at 0x1100. The first 2048 bytes (0x1100–0x18FF) is mirrored at 0x0200–0x09FF for compatibility. Also, some recent models bend the 8-bit and 16-bit peripheral rules, allowing 16-bit access to peripherals in the 8-bit peripheral address range.
There is a new extended version of the architecture (called MSP430X) which allows a 20-bit address space
. It allows additional program ROM beginning at 0x10000.
The '5xx series has a greatly redesigned address space, with the first 4K devoted to peripherals, and up to 16K of RAM.
The MSP430 family defines 11 I/O ports, P0 through P10, although no chip implements more than 10 of them. P0 is only implemented on the '3xx family. P7 through P10 are only implemented on the largest members (and highest pin count versions) of the '4xx and '2xx families. The newest '5xx and '6xx families has P1 through P11, and the control registers are reassigned to provide more port pairs.
Each port is controlled by the following registers. Ports which do not implement particular features (such as interrupt on state change) do not implement the corresponding registers.
PxIN : Port x input. This is a read-only register, and reflects the current state of the port's pins.
PxOUT : Port x output. The values written to this read/write register are driven out the corresponding pins when they are configured to output.
PxDIR : Port x data direction. Bits written as 1 configure the corresponding pin for output. Bits written as 0 configure the pin for input.
PxSEL : Port x function select. Bits written as 1 configure the corresponding pin for use by the specialized peripheral. Bits written as 0 configure the pin for general-purpose I/O. Port 0 ('3xx parts only) is not multiplexed with other peripherals and does not have a P0SEL register.
PxREN : Port x resistor enable ('2xx & '5xx only). Bits set in this register enable weak pull-up
or pull-down resistors on the corresponding I/O pins even when they are configured as inputs. The direction of the pull is set by the bit written to the PxOUT register.
PxDS : Port x drive strength ('5xx only). Bits set in this register enable high-current outputs. This increases output power, but may cause EMI
.
Ports 0–2 can produce interrupts when inputs change. Additional registers configure this ability:
PxIES : Port x interrupt edge select. Selects the edge which will cause the PxIFG bit to be set. When the input bit changes from matching the PxIES state to not matching it (i.e. whenever a bit in PxIES XOR PxIN changes from clear to set), the corresponding PxIFG bit is set.
PxIE : Port x interrupt enable. When this bit and the corresponding PxIFG bit are both set, an interrupt is generated.
PxIFG : Port x interrupt flag. Set whenever the corresponding pin makes the state change requested by PxIES. Can be cleared only by software. (Can also be set by software.)
PxIV : Port x interrupt vector ('5xx only). This 16-bit register is a priority encoder
which can be used to handle pin-change interrupts. If n is the lowest-numbered interrupt bit which is pending in PxIFG and enabled in PxIE, this register reads as 2n+2. If there is no such bit, it reads as 0. The scale factor of 2 allows direct use as an offset into a branch table
. Reading this register also clears the reported PxIFG flag.
Some pins have special purposes either as inputs or outputs. (For example, timer pins can be configured as capture inputs or PWM outputs.) In this case, the PxDIR bit controls which of the two functions the pin performs when the PxSEL bit is set. If there is only one special function, then PxDIR is generally ignored.
The PxIN register is still readable if the PxSEL bit is set, but interrupt generation is disabled. If PxSEL is clear, the special function's input is frozen and disconnected from the external pin. Also, configuring a pin for general-purpose output does not disable interrupt generation.
The MSP430 line offers two types of Analog-to-Digital Conversion (ADC). 10- and 12-bit Successive Approximation converters, as well as a 16-bit Sigma-Delta converter. Data transfer controllers and a 16 word conversion-and-control buffer allow the MSP430 to convert and store samples without CPU intervention, minimizing power consumption.
Brown Out Reset
The Brown Out Reset circuitry detects low supply voltages and initiates a POR (Power On Reset) signal to reset the device. The MSP430's BOR circuit uses almost no power and is enabled at all times, including in all low power modes.
Comparator A, A+
The MSP430's comparator module provides precision slope Analog-to-Digital Conversions. Monitors external analog signals and provides voltage and resistor value measurement. Capable of selectable power modes.
Digital-to-Analog Converter
The MSP430's Digital-to-Analog Converter
module features 8- and 12-bit modes and a programmable settling time for low power optimization. Internal or external reference selection is also possible.
Timers
The MSP 430 has 1 or 2 relatively flexible timers (5xxx series has 3). Each timer has 3 to 7 capture and compare registers that can each be observing the timer count and take a snap shot due to the change in an external signal or cause an external signal to change at a specified timer count. One of the timers can get its clock from an external signal. Timer clocks can not be gated or started and stopped by external signals. The ability to chain timers together to produce complex pulse sequences is limited. Interrupt generation is very flexible.
Direct Memory Access Controller
The MSP430's DMA allows data transfers from one address to another without CPU intervention, across the entire address range. Features up to three independent transfer channels.
Although the MSP430's DMA subsystem is very capable it has several flaws, the most significant of which is the lack of an external transfer strobe. Although a DMA transfer can be triggered externally, there is no external indication of completion of a transfer. Consequently DMA to and from external sources is limited to external trigger per byte transfers, rather than full blocks automatically via DMA. This can lead to significant complexity (as in requiring extensive hand tweaking of code) when implementing processor to processor or processor to USB communications. The reference cited uses an obscure timer mode to generate high speed strobes for DMA transfers. Unfortunately, the timers are not flexible enough to easily make up for the lack of an external DMA transfer strobe.
DMA operations that involve word transfers to byte locations cause truncation to 8 bits rather than conversion to two byte transfers. This makes DMA with A/D or D/A 16 bit values less useful than it could be (although it is possible to DMA these values through port A or B on some versions of the MSP 430 using an externally visible trigger per transfer such as a timer output).
ESP430 (integrated in FE42xx devices)
The ESP430CE module performs metering calculations independent of the CPU. Module has separate SD15, HW multiplier, and embedded processor engine.
LCD/LCD_A/LCD_B
The LCD/LCD_A controller directly drives LCD displays for up to 196 segments. Supports static, 2-mux, 3-mux, and 4-mux LCDs. LCD_A module has integrated charge pump for contrast control. LCD_B enables blinking of individual segments with separate blinking memory.
Op Amps
Feature single supply, low current operation with rail-to-rail outputs and programmable settling times. Software selectable configuration options: unity gain mode, comparator mode, inverting PGA, non-inverting PGA, differential and instrumentation amplifier.
Hardware multiplier
Some MSP430 models include a memory-mapped hardware multiplier peripheral which performs various 16×16+32→33-bit multiply-accumulate operations. Unusually for the MSP430, this peripheral does include an implicit 2-bit write-only register, which makes it effectively impossible to context switch
.
The 8 registers used are:
The first operand is written to one of four 16-bit registers. The address written determines the operation performed. While the value written can be read back from any of the registers, the register number written to cannot be recovered.
If a multiply-accumulate operation is desired, the
Then, each time a write is performed to the
The result is available after three clock cycles of delay, which is the time required to fetch a following instruction and a following index word. Thus, the delay is typically invisible. An explicit delay is only required if using an indirect addressing mode to fetch the result.
C/C++ compiler
and Integrated development environment
, or IDE. A Kickstart edition can be downloaded for free from TI or IAR; it is limited to 8 KB of C/C++ code in the compiler and debugger
(assembly language
programs of any size can be developed and debugged with this free toolchain).
TI also combines a version of its own compiler and tools with its Eclipse
-based Code Composer Studio
IDE ("CCS"). It sells full-featured versions, and offers a free version for download which has a code size limit of 16 KB. CCS supports in-circuit emulators, and includes a simulator and other tools; it can also work with other processors sold by TI.
The open source
community produces a freely available software development toolset based on the GNU toolset
.
The GNU compiler is currently declined in three versions:
(MSPGCC)
(MSPGCC 4.x)
(MSPGCC Uniarch)
There is very early llvm-msp430 project, which may eventually provide better support for MSP430 in LLVM.
Other commercial development tool sets, which include editor, compiler, linker, assembler, debugger and in some cases code wizards, are available. VisSim
, a block diagram
language for model based development, generates efficient fixed point
C-Code directly from the diagram. VisSim generated code for a closed loop
ADC+PWM based PID control on the F2013 compiles to less than 1 KB flash and 100 bytes RAM. VisSim has on-chip peripheral blocks for the entire MSP430 family I2C, ADC, SD16, PWM.
The MSP430F2013 and its siblings are set apart by the fact that (except for the MSP430G2 Value Line) it is the only MSP430 part that is available in a dual in-line package
(DIP). Other variants in this family are only available in various surface-mount packages. TI has gone to some trouble to support the eZ430 development platform by making the raw chips easily prototypable by hobbyists.
Texas Instruments
released the MSP430 Launchpad in July 2010 at the price of $4.30 with free shipping. The MSP430 Launchpad has an onboard flash emulator, USB, 2 programmable LED
s, and 1 programmable push button.
at the MSP430 Launchpad wiki.
The advantage of the Spy-Bi-Wire protocol is that it uses only two communication lines, one of which is the dedicated _RESET line. The JTAG interface on the lower pin count MSP430 parts is multiplexed with general purpose I/O lines. This makes it relatively difficult to debug circuits built around the small, low-I/O-budget chips, since the full 4-pin JTAG hardware will conflict with anything else connected to those I/O lines. This problem is alleviated with the Spy-Bi-Wire-capable chips, which are still compatible with the normal JTAG interface for backwards compatibility with the old development tools.
JTAG debugging and flash programming tools based on OpenOCD and widely used in the ARM community are not available for the MSP430. Programming tools specially designed for the MSP430 are marginally less expensive than JTAG interfaces that use OpenOCD. However, should a project discover midstream that more MIPS, more memory, and more I/O peripherals are needed, those tools will not transfer to a processor from another vendor.
Mixed-signal integrated circuit
A mixed-signal integrated circuit is any integrated circuit that has both analog circuits and digital circuits on a single semiconductor die.- Examples :...
microcontroller
Microcontroller
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM...
family from Texas Instruments
Texas Instruments
Texas Instruments Inc. , widely known as TI, is an American company based in Dallas, Texas, United States, which develops and commercializes semiconductor and computer technology...
. Built around a 16-bit
16-bit
-16-bit architecture:The HP BPC, introduced in 1975, was the world's first 16-bit microprocessor. Prominent 16-bit processors include the PDP-11, Intel 8086, Intel 80286 and the WDC 65C816. The Intel 8088 was program-compatible with the Intel 8086, and was 16-bit in that its registers were 16...
CPU, the MSP430 is designed for low cost, and specifically, low power consumption embedded applications. The architecture dates from the 1990s and is reminiscent of the DEC PDP-11
PDP-11 architecture
The PDP-11 architecture is an instruction set architecture developed by Digital Equipment Corporation . It is implemented by central processing units and microprocessors used in minicomputers of the same name. Additional information is found in DEC's PDP-11 Processor Handbook .-Memory...
.
Applications
The MSP430 is a popular choice among hardware designers for low powered embedded devices. The electric currentElectric current
Electric current is a flow of electric charge through a medium.This charge is typically carried by moving electrons in a conductor such as wire...
drawn in idle mode can be less than 1 microamp. The top CPU speed is 25 MHz. It can be throttled back for lower power consumption. The MSP430 also utilizes six different Low-Power Modes, which can disable unneeded clocks and CPU. This allows the MSP430 to sleep, while its peripheral
Peripheral
A peripheral is a device attached to a host computer, but not part of it, and is more or less dependent on the host. It expands the host's capabilities, but does not form part of the core computer architecture....
s continue to work without the need for an energy hungry processor
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
. Additionally, the MSP430 is capable of wake-up times below 1 microsecond, allowing the microcontroller to stay in sleep mode longer, minimizing its average current consumption. Note that MHz is not equivalent to Million instructions per second (MIPS), and different architectures can obtain different MIPS rates at lower CPU clock frequencies, which can result in lower dynamic power consumption for an equivalent amount of digital processing.
The device comes in a variety of configurations featuring the usual peripherals: internal oscillator, timer
Timer
A timer is a specialized type of clock. A timer can be used to control the sequence of an event or process. Whereas a stopwatch counts upwards from zero for measuring elapsed time, a timer counts down from a specified time interval, like an hourglass.Timers can be mechanical, electromechanical,...
including PWM
Pulse-width modulation
Pulse-width modulation , or pulse-duration modulation , is a commonly used technique for controlling power to inertial electrical devices, made practical by modern electronic power switches....
, watchdog
Watchdog timer
A watchdog timer is a computer hardware or software timer that triggers a system reset or other corrective action if the main program, due to some fault condition, such as a hang, neglects to regularly service the watchdog A watchdog timer (or computer operating properly (COP) timer) is a computer...
, USART, SPI
Serial Peripheral Interface Bus
The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select ...
, I2C, 10/12/14/16-bit ADC
Analog-to-digital converter
An analog-to-digital converter is a device that converts a continuous quantity to a discrete time digital representation. An ADC may also provide an isolated measurement...
s, and brownout
Brownout (electricity)
A brownout is an intentional drop in voltage in an electrical power supply system used for load reduction in an emergency. The reduction lasts for minutes or hours, as opposed to short-term voltage sag or dip. The term brownout comes from the dimming experienced by lighting when the voltage sags...
reset circuitry. Some less usual peripheral options include comparator
Comparator
In electronics, a comparator is a device that compares two voltages or currents and switches its output to indicate which is larger. They are commonly used in devices such as Analog-to-digital converters .- Input voltage range :...
s (that can be used with the timers to do simple ADC), on-chip op-amp
Operational amplifier
An operational amplifier is a DC-coupled high-gain electronic voltage amplifier with a differential input and, usually, a single-ended output...
s for signal conditioning
Signal conditioning
In electronics, signal conditioning means manipulating an analog signal in such a way that it meets the requirements of the next stage for further processing...
, 12-bit DAC
Digital-to-analog converter
In electronics, a digital-to-analog converter is a device that converts a digital code to an analog signal . An analog-to-digital converter performs the reverse operation...
, LCD
Liquid crystal display
A liquid crystal display is a flat panel display, electronic visual display, or video display that uses the light modulating properties of liquid crystals . LCs do not emit light directly....
driver, hardware multiplier, USB, and DMA
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....
for ADC results. Apart from some older EPROM
EPROM
An EPROM , or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages...
(PMS430E3xx) and high volume mask ROM
Mask ROM
Mask ROM is a type of read-only memory whose contents are programmed by the integrated circuit manufacturer...
(MSP430Cxxx) versions, all of the devices are in-system programmable
In-System Programming
In-System Programming is the ability of some programmable logic devices, microcontrollers, and other programmable electronic chips to be programmed while installed in a complete system, rather than requiring the chip to be programmed prior to installing it into the system.The primary advantage of...
via JTAG
JTAG
Joint Test Action Group is the common name for what was later standardized as the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for testing printed circuit boards using boundary scan and is still widely used for this application.Today JTAG is also...
(full four-wire or Spy-Bi-Wire
Spy-Bi-Wire
Spy-Bi-Wire is a serialised JTAG protocol developed by Texas Instruments for their MSP430 micro controllers.In this protocol only two connections are used instead of the usual four pins for the general JTAG interface. The two connections are a bidirectional data output, and a clock...
) or a built in bootstrap loader (BSL) using RS-232
RS-232
In telecommunications, RS-232 is the traditional name for a series of standards for serial binary single-ended data and control signals connecting between a DTE and a DCE . It is commonly used in computer serial ports...
.
There are, however, limitations that preclude its use in more complex embedded systems. The MSP430 does not have an external memory bus
Memory bus
The memory bus is the computer bus which connects the main memory to the memory controller in computer systems. Originally, general-purpose buses like VMEbus and the S-100 bus were used, but to reduce latency, modern memory buses are designed to connect directly to DRAM chips, and thus are...
, so is limited to on-chip memory (up to 256 KB Flash memory
Flash memory
Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM and must be erased in fairly large blocks before these can be rewritten with new data...
and 16 KB RAM
Random-access memory
Random access memory is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order with a worst case performance of constant time. Strictly speaking, modern types of DRAM are therefore not random access, as data is read in...
) which might be too small for applications that require large buffers or data tables. Also, although it has a very capable DMA controller, it is very difficult to use it to move data off the chip due to a lack of a DMA output strobe.
MSP430 part numbering
An MSP430 part number such as "MSP430FG4619IZQWR" consists of the following pieces:- MSP430: Standard prefix.(4th month 30th day).
- F: A letter indicating the type ROM. "F" indicating flash ROM is by far the most popular. Other options are "C" for masked ROM, "E" for UV-eraseable EPROMEPROMAn EPROM , or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages...
and "P" for one-time programmable ROMProgrammable read-only memoryA programmable read-only memory or field programmable read-only memory or one-time programmable non-volatile memory is a form of digital memory where the setting of each bit is locked by a fuse or antifuse. Such PROMs are used to store programs permanently...
. "L" as in the MSP430L09x series indicates a RAM-only part; it must remain continuously powered to retain its programming. - G: An optional specialization letter indicating hardware support for a specialized use. "E" indicates special electricity meter functions, "G" devices are designed for medical instrumentation, and "W" devices include a special "scan interface" designed for flow meters. An exception is the MSP430FG2xx devices, which are considered a separate generation.
- 4: The generation of device. There can be significant changes to core peripherals (clock generators, UARTs, etc.) in different generations. These are not in chronological order, but rather higher values roughly indicate greater size, complexity and cost. For example, generations 3 and 4 include LCD display controllers which the others do not.
- 6: The model within the generation. This indicates the mixture of on-board peripheral devices and number of pins.
- 19: One or two digits indicating the amount of memory on the device. The numbering is (mostly) consistent throughout the MSP430 series. Not all suffixes are valid with all models; most models are available in 3–6 memory sizes, chosen to match the other capabilities of the device. Larger numbers indicate increasing amounts of memory, but sometimes one type of memory (RAM or ROM) is sacrificed to fit more of the other.
- An optional suffix digit indicating a variant device, adding or deleting some analog peripherals. For example, a "1" suffix may indicate the addition of a comparator or deletion of an ADC. If the memory size is "1", this suffix can be confused with part of the memory size, but no single model is available in both "1" and "10" (or greater) memory sizes.
- An optional "A" suffix indicating an upward-compatible revised version. The MSP430F11x1A has an additional 256 bytes of data flash not present in the plain 'F11x1.
Trailing suffix letters indicate options not visible to software:
- I: Indicates support for the "Industrial" (−40 to +85 °C) temperature range.
- ZQW: Indicates the package the part is kept in. "ZQW" is a TI-specific name for a ball grid arrayBall grid arrayA ball grid array is a type of surface-mount packaging used for integrated circuits.- Description :The BGA is descended from the pin grid array , which is a package with one face covered with pins in a grid pattern. These pins conduct electrical signals from the integrated circuit to the printed...
. - R: Indicates that the parts are shipped in tape and reel packaging for use by pick-and-place machines.
MSP430 generations
There are five general generations of MSP430 processors. In order of development, they were the '3xx generation, the '1xx generation, the '4xx generation, the '2xx generation, and the '5xx generation. The digit after the generation identifies the model (generally higher model numbers are larger and more capable), the third digit identifies the amount of memory on board, and the fourth, if present, identifies a minor model variant. The most common variation is a different on-chip analog-to-digital converterAnalog-to-digital converter
An analog-to-digital converter is a device that converts a continuous quantity to a discrete time digital representation. An ADC may also provide an isolated measurement...
.
The 3xx and 1xx generations were limited to a 16 bit address space. In the later generations this was expanded to include '430X' instructions that allow a 20 bit address space. As happened with the PDP-11, and as one might expect, extending the addressing range beyond the 16 bit word size introduced some peculiarities and inefficiencies for programs larger than 64 kBytes.
In the following list, it helps to think of the typical 200 mA·Hr capacity of a CR2032 lithium coin cell as 200,000 μA·Hr, or 22.8 μA·year. Thus, considering only the CPU draw, such a battery could supply a 0.7 μA current draw for 32 years. (In reality, battery self-discharge
Self-discharge
Self-discharge is a phenomenon in batteries in which internal chemical reactions reduce the stored charge of the battery without any connection between the electrodes...
would reduce this number.)
The significance of the 'RAM retention' vs the 'real-time clock mode' is that in real time clock mode the CPU can go to sleep with a clock running which will wake it up at a specific future time. In RAM retention mode, some external signal is required to wake it, e.g. I/O pin signal or SPI slave receive interrupt.
MSP430x1xx Series
The MSP430x1xx Series is the basic generation without an embedded LCD controller. They are generally smaller than the '3xx generation. These Flash or ROM based Ultra-Low Power MCUs offer 8 MIPS, 1.8–3.6 V operation, up to 60 KB Flash, and a wide range of high-performance analog and intelligent digital peripherals.- Power specs - As low as
- 0.1 μA RAM retention
- 0.7 μA real-time clock mode
- 200 μA / MIPS active
- Feature Fast Wake-Up From Standby Mode in <6 μs
- Device Parameters
- Flash Options: 1–60 KiB
- ROM Options: 1–16 KiB
- RAM Options: 512 B–10 KiB
- GPIO Options: 14, 22, 48 pins
- ADC Options: Slope, 10 & 12-bit SAR
- Other Integrated peripherals: Analog Comparator, DMA, Hardware Multiplier, SVS, 12-bit DAC
MSP430F2xx Series
The MSP430F2xx Series are similar to the '1xx generation, but operate at even lower power, support up to 16 MHz operation, and have a more accurate (±2%) on-chip clock that makes it easier to operate without an external crystal. These Flash-based Ultra-Low Power offer 1.8–3.6 V operation. Includes the Very-Low power Oscillator (VLO), internal pull-up/pull-down resistors, and low-pin count options.- Power Specs Overview, as low as:
- 0.1 μA RAM retention
- 0.3 μA Standby mode (VLO)
- 0.7 μA real-time clock mode
- 220 μA / MIPS active
- Feature Ultra-Fast Wake-Up From Standby Mode in <1 μs
- Device Parameters
- Flash Options: 1–120 KiB
- RAM Options: 128 B–8 KiB
- GPIO Options: 10, 16, 24, 32, 48, 64 pins
- ADC Options: Slope, 10 & 12-bit SAR, 16-bit Sigma Delta
- Other Integrated peripherals: Analog Comparator, Hardware Multiplier, DMA, SVS, 12-bit DAC, Op Amps
MSP430G2xx Series
The MSP430G2xx Value Series features flash-based Ultra-Low Power MCUs up to 16 MIPS with 1.8–3.6 V operation. Includes the Very-Low power Oscillator (VLO), internal pull-up/pull-down resistors, and low-pin count options, at lower prices than the MSP430F2xx series.- Ultra-Low Power, as low as (@2.2V):
- 0.1 μA RAM retention
- 0.4 μA Standby mode (VLO)
- 0.7 μA real-time clock mode
- 220 μA / MIPS active
- Ultra-Fast Wake-Up From Standby Mode in <1 μs
- Device Parameters
- Flash Options: 0.5–16 KiB
- RAM Options: 128–512 B
- GPIO Options: 10, 16, 24 pins
- ADC Options: Slope, 10-bit SAR
- Other Integrated peripherals: Analog Comparator, Temp sensor
MSP430x3xx Series
The MSP430x3xx Series is the oldest generation, designed for portable instrumentation with an embedded LCD controller. This also includes a frequency-locked loopFrequency-locked loop
A frequency-lock, or frequency-locked loop , is an electronic control system that generates a signal that is locked to the frequency of an input or "reference" signal...
oscillator that can automatically synchronize to a low-speed (32 kHz) crystal. This generation does not support EEPROM
EEPROM
EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed, e.g., calibration...
memory, only mask ROM and UV-eraseable and one-time programmable EPROM
EPROM
An EPROM , or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages...
. Later generations provide only flash ROM and mask ROM
Mask ROM
Mask ROM is a type of read-only memory whose contents are programmed by the integrated circuit manufacturer...
options. These devices offer 2.5–5.5 V operation, up to 32 KB ROM.
- Power Specs Overview, as low as:
- 0.1 μA RAM retention
- 0.9 μA real-time clock mode
- 160 μA / MIPS active
- Feature Fast Wake-Up From Standby Mode in <6 μs
- Device Parameters
- ROM Options: 2–32 KB
- RAM Options: 512 B–1 KiB
- GPIO Options: 14, 40 pins
- ADC Options: Slope, 14-bit SAR
- Other Integrated peripherals: LCD controller, Hardware Multiplier
MSP430x4xx Series
The MSP430x4xx Series are similar to the '3xx generation, and also include an integrated LCD controller, but are larger and more capable. These Flash or ROM based devices offers 8–16 MIPS at 1.8–3.6 V operation, with FLL, and SVS. Ideal for low power metering and medical applications.- Power Specs Overview, as low as:
- 0.1 μA RAM retention
- 0.7 μA real-time clock mode
- 200 μA / MIPS active
- Feature Fast Wake-Up From Standby Mode in <6 μs
- Device Parameters
- Flash/ROM Options: 4 kB – 120 KB
- RAM Options: 256 B – 8 KB
- GPIO Options: 14, 32, 48, 56, 68, 72, 80 pins
- ADC Options: Slope, 10 &12-bit SAR, 16-bit Sigma Delta
- Other Integrated peripherals: LCD Controller, Analog Comparator, 12-bit DAC, DMA, Hardware Multiplier, Op Amp, USCI Modules
MSP430x5xx Series
The MSP430x5xx Series are able to run up to 25 MHz, have up to 256 kB flash memory and up to 16 kB RAM. This new Flash-based family features the lowest active power consumption with up to 25 MIPS at 1.8-3.6 V operation (165 uA/MIPS). Includes an innovative Power Management Module for optimal power consumption. Many devices feature integrated USB.- Power Specs Overview, as low as:
- 0.1 μA RAM retention
- 2.5 μA real-time clock mode
- 165 μA / MIPS active
- Feature Fast Wake-Up From Standby Mode in <5 μs
- Device Parameters:
- Flash Options: up to 256 KB
- RAM Options: up to 16 KB
- ADC Options: 10 & 12-bit SAR
- Other Integrated peripherals: USB, Analog Comparator, DMA, Hardware Multiplier, RTC, USCI, 12-bit DAC
Note that when the flash size is over 64K words (128 KBytes), instruction addresses can no longer be encoded in just two bytes. This change in pointer size causes some incompatibilities with previous parts.
MSP430 CPU
The MSP430 CPU uses a von Neumann architectureVon Neumann architecture
The term Von Neumann architecture, aka the Von Neumann model, derives from a computer architecture proposal by the mathematician and early computer scientist John von Neumann and others, dated June 30, 1945, entitled First Draft of a Report on the EDVAC...
, with a single address space for instructions and data. Memory is byte
Byte
The byte is a unit of digital information in computing and telecommunications that most commonly consists of eight bits. Historically, a byte was the number of bits used to encode a single character of text in a computer and for this reason it is the basic addressable element in many computer...
-addressed, and pairs of bytes are combined little-endian to make 16-bit words.
The processor contains 16 16-bit registers, of which 4 are dedicated to special purposes: R0 is the program counter
Program counter
The program counter , commonly called the instruction pointer in Intel x86 microprocessors, and sometimes called the instruction address register, or just part of the instruction sequencer in some computers, is a processor register that indicates where the computer is in its instruction sequence...
, R1 is the stack pointer, R2 is the status register
Status register
A status register or flag register is a collection of flag bits for a processor. An example is the FLAGS register of the x86 architecture....
, and R3 is a special register called the constant generator, providing access to 6 commonly used constant values without requiring an additional operand. R3 always reads as 0 and writes to it are ignored. R4 through R15 are available for general use.
The instruction set is very simple; there are 27 instructions in three families. Most instructions are available in .B (8-bit byte) and .W (16-bit word) suffixed versions, depending on the value of a B/W bit: the bit is set to 1 for 8-bit and 0 for 16-bit. A missing suffix is equivalent to .W. Byte operations to memory affect only the addressed byte, while byte operations to registers clear the most significant byte.
| 15 | | 14 | | 13 | | 12 | 11 | | 10 | | 9 | | 8 | 7 | | 6 | | 5 | | 4 | 3 | | 2 | | 1 | | 0 | Instruction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 0 | opcode | B/W | As | register | Single-operand arithmetic | ||||||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | B/W | As | register | RRC Rotate right (1 bit) through carry | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | As | register | SWPB Swap bytes | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | B/W | As | register | RRA Rotate right (1 bit) arithmetic | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | As | register | SXT Sign extend byte to word | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | B/W | As | register | PUSH Push value onto stack | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | As | register | CALL Subroutine call; push PC and move source to PC | ||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | RETI Return from interrupt; pop SR then pop PC |
| 0 | 0 | 1 | condition | 10-bit signed offset | Conditional jump; PC = PC + 2×offset | |||||||||||
| 0 | 0 | 1 | 0 | 0 | 0 | 10-bit signed offset | JNE/JNZ Jump if not equal/zero | |||||||||
| 0 | 0 | 1 | 0 | 0 | 1 | 10-bit signed offset | JEQ/JZ Jump if equal/zero | |||||||||
| 0 | 0 | 1 | 0 | 1 | 0 | 10-bit signed offset | JNC/JLO Jump if no carry/lower | |||||||||
| 0 | 0 | 1 | 0 | 1 | 1 | 10-bit signed offset | JC/JHS Jump if carry/higher or same | |||||||||
| 0 | 0 | 1 | 1 | 0 | 0 | 10-bit signed offset | JN Jump if negative | |||||||||
| 0 | 0 | 1 | 1 | 0 | 1 | 10-bit signed offset | JGE Jump if greater or equal | |||||||||
| 0 | 0 | 1 | 1 | 1 | 0 | 10-bit signed offset | JL Jump if less | |||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | 10-bit signed offset | JMP Jump (unconditionally) | |||||||||
| opcode | source | Ad | B/W | As | destination | Two-operand arithmetic | ||||||||||
| 0 | 1 | 0 | 0 | source | Ad | B/W | As | destination | MOV Move source to destination | |||||||
| 0 | 1 | 0 | 1 | source | Ad | B/W | As | destination | ADD Add source to destination | |||||||
| 0 | 1 | 1 | 0 | source | Ad | B/W | As | destination | ADDC Add source and carry to destination | |||||||
| 0 | 1 | 1 | 1 | source | Ad | B/W | As | destination | SUBC Subtract source from destination (with carry) | |||||||
| 1 | 0 | 0 | 0 | source | Ad | B/W | As | destination | SUB Subtract source from destination | |||||||
| 1 | 0 | 0 | 1 | source | Ad | B/W | As | destination | CMP Compare (pretend to subtract) source from destination | |||||||
| 1 | 0 | 1 | 0 | source | Ad | B/W | As | destination | DADD Decimal Binary-coded decimal In computing and electronic systems, binary-coded decimal is a digital encoding method for numbers using decimal notation, with each decimal digit represented by its own binary sequence. In BCD, a numeral is usually represented by four bits which, in general, represent the decimal range 0 through 9... add source to destination (with carry) |
|||||||
| 1 | 0 | 1 | 1 | source | Ad | B/W | As | destination | BIT Test bits of source AND destination | |||||||
| 1 | 1 | 0 | 0 | source | Ad | B/W | As | destination | BIC Bit clear (dest &= ~src) | |||||||
| 1 | 1 | 0 | 1 | source | Ad | B/W | As | destination | BIS Bit set (logical OR) | |||||||
| 1 | 1 | 1 | 0 | source | Ad | B/W | As | destination | XOR Exclusive or source with destination | |||||||
| 1 | 1 | 1 | 1 | source | Ad | B/W | As | destination | AND Logical AND source with destination (dest &= src) | |||||||
Instructions are 16 bits, followed by up to two 16-bit extension words. Addressing modes are specified by the 2-bit As field and the 1-bit Ad field. Some special versions can be constructed using R0, and modes other than register direct using R2 (the status register) and R3 (the constant generator) are interpreted specially. Ad can use only a subset of the addressing modes for As.
Indexed addressing modes add a 16-bit extension word to the instruction. If both source and destination are indexed, the source extension word comes first. x refers to the next extension word in the instruction stream in the table below.
| As | Ad | Register | Syntax | Description |
|---|---|---|---|---|
| 00 | 0 | n | Rn | Register direct. The operand is the contents of Rn. |
| 01 | 1 | n | x(Rn) | Indexed. The operand is in memory at address Rn+x. |
| 10 | - | n | @Rn | Register indirect. The operand is in memory at the address held in Rn. |
| 11 | - | n | @Rn+ | Indirect autoincrement. As above, then the register is incremented by 1 or 2. |
| Addressing modes using R0 (PC) | ||||
| 01 | 1 | 0 (PC) | ADDR | Symbolic. Equivalent to x(PC). The operand is in memory at address PC+x. |
| 11 | - | 0 (PC) | #x | Immediate. Equivalent to @PC+. The operand is the next word in the instruction stream. |
| Addressing modes using R2 (SR) and R3 (CG), special-case decoding | ||||
| 01 | 1 | 2 (SR) | &ADDR | Absolute. The operand is in memory at address x. |
| 10 | - | 2 (SR) | #4 | Constant. The operand is the constant 4. |
| 11 | - | 2 (SR) | #8 | Constant. The operand is the constant 8. |
| 00 | - | 3 (CG) | #0 | Constant. The operand is the constant 0. |
| 01 | - | 3 (CG) | #1 | Constant. The operand is the constant 1. There is no index word. |
| 10 | - | 3 (CG) | #2 | Constant. The operand is the constant 2. |
| 11 | - | 3 (CG) | #−1 | Constant. The operand is the constant −1. |
Instructions generally take 1 cycle per word fetched or stored, so instruction times range from 1 cycle for a simple register-register instruction to 6 cycles for an instruction with both source and destination indexed.
The MSP430X extension with 20-bit addressing adds additional instructions that can require up to 10 clock cycles. Setting or clearing a peripheral bit takes two clocks. A jump, taken or not takes two clocks. With the 2xx series 2 MCLKs is 125 ns at 16 MHz.
Moves to the program counter are allowed and perform jumps. Return from subroutine, for example, is implemented as MOV @SP+,PC.
When R0 (PC) or R1 (SP) are used with the autoincrement addressing mode, they are always incremented by two. Other registers (R4 through R15) are incremented by the operand size, either 1 or 2 bytes.
The status register contains 4 arithmetic status bits, a global interrupt enable, and 4 bits that disable various clocks to enter low-power mode. When handling an interrupt, the processor saves the status register on the stack and clears the low-power bits. If the interrupt handler does not modify the saved status register, returning from the interrupt will then resume the original low-power mode.
Pseudo-operations
A number of additional instructions are implemented as aliases for forms of the above. For example, there is no specific "return from subroutine" instruction, but it is implemented as "MOV @SP+,PC". Emulated instructions are:| Emulated | Actual | Description |
|---|---|---|
| ADC.x dst | ADDC.x #0,dst | Add carry to destination |
| BR dst | MOV dst,PC | Branch to destination |
| CLRC | BIC #1,SR | Clear carry bit |
| CLRN | BIC #4,SR | Clear negative bit |
| CLRZ | BIC #2,SR | Clear zero bit |
| DADC.x dst | DADD.x #0,dst | Decimal add carry to destination |
| DEC.x dst | SUB.x #1,dst | Decrement |
| DECD.x dst | SUB.x #2,dst | Double decrement |
| DINT | BIC #8,SR | Disable interrupts |
| EINT | BIS #8,SR | Enable interrupts |
| INC.x dst | ADD.x #1,dst | Increment |
| INCD.x dst | ADD.x #2,dst | Double increment |
| INV.x dst | XOR.x #−1,dst | Invert |
| NOP | MOV #0,R3 | No operation |
| POP dst | MOV @SP+,dst | Pop from stack |
| RET | MOV @SP+,PC | Return from subroutine |
| RLA.x dst | ADD.x dst,dst | Rotate left arithmetic (shift left 1 bit) |
| RLC.x dst | ADDC.x dst,dst | Rotate left through carry |
| SBC.x dst | SUBC.x #0,dst | Subtract borrow (1−carry) from destination |
| SETC | BIS #1,SR | Set carry bit |
| SETN | BIS #4,SR | Set negative bit |
| SETZ | BIS #2,SR | Set zero bit |
| TST.x dst | CMP.x #0,dst | Test destination |
Note that the immediate constants −1 (0xffff), 0, 1, 2, 4 and 8 can be specified in a single-word instruction without needing a separate immediate operand.
MSP430X 20-bit extension
The basic MSP430 cannot support more memory (ROM + RAM + peripherals) than its 64K address space. In order to support this, an extended form of the MSP430 uses 20-bit registers and a 20-bit address space, allowing up to 1 MB of memory. This uses the same instruction set as the basic form, but with two extensions:- A limited number of 20-bit instructions for common operations, and
- A general prefix-word mechanism that can extend any instruction to 20 bits.
The extended instructions include some additional capabilities, notably multi-bit shifts and multi-register load/store operations.
20-bit operations use the length suffix ".A" (for address) instead of .B or .W. .W is still the default. In general, shorter operations clear the high-order bits of the destination register.
The new instructions are as follows:
| 15 | | 14 | | 13 | | 12 | 11 | | 10 | | 9 | | 8 | 7 | | 6 | | 5 | | 4 | 3 | | 2 | | 1 | | 0 | Second word | Instruction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | source | 0 | 0 | opcode | destination | Extended memory-register moves | ||||||||
| 0 | 0 | 0 | 0 | src | 0 | 0 | 0 | 0 | dst | — | MOVA @Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 0 | 0 | 0 | 1 | dst | — | MOVA @Rsrc+,Rdst | ||||||
| 0 | 0 | 0 | 0 | addr[19:16] | 0 | 0 | 1 | 0 | dst | addr[15:0] | MOVA &abs20,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 0 | 0 | 1 | 1 | dst | x[15:0] | MOVA x(Rsrc),Rdst | ||||||
| 0 | 0 | 0 | 0 | n−1 | op. | 0 | 1 | 0 | W/A | destination | Bit shifts (1–4 bit positions) | ||||||
| 0 | 0 | 0 | 0 | n−1 | 0 | 0 | 0 | 1 | 0 | W/A | dst | — | RRCM.x #n,Rdst (Rotate right through carry.) | ||||
| 0 | 0 | 0 | 0 | n−1 | 0 | 1 | 0 | 1 | 0 | W/A | dst | — | RRAM.x #n,Rdst (Rotate right arithmetic, a.k.a. shift right signed.) | ||||
| 0 | 0 | 0 | 0 | n−1 | 1 | 0 | 0 | 1 | 0 | W/A | dst | — | RLAM.x #n,Rdst (Rotate left arithmetic, a.k.a. shift left.) | ||||
| 0 | 0 | 0 | 0 | n−1 | 1 | 1 | 0 | 1 | 0 | W/A | dst | — | RRUM.x #n,Rdst (Rotate right unsigned, a.k.a. shift right logical.) | ||||
| 0 | 0 | 0 | 0 | source | 0 | 1 | 1 | op. | destination | Extended register-memory moves | |||||||
| 0 | 0 | 0 | 0 | src | 0 | 1 | 1 | 0 | addr[19:16] | addr[15:0] | MOVA Rsrc,&abs20 | ||||||
| 0 | 0 | 0 | 0 | src | 0 | 1 | 1 | 1 | dst | x[15:0] | MOVA Rsrc,x(Rdst) | ||||||
| 0 | 0 | 0 | 0 | source | 1 | opcode | destination | Extended ALU operations | |||||||||
| 0 | 0 | 0 | 0 | imm[19:16] | 1 | 0 | 0 | 0 | dst | imm[15:0] | MOVA #imm20,Rdst | ||||||
| 0 | 0 | 0 | 0 | imm[19:16] | 1 | 0 | 0 | 1 | dst | imm[15:0] | CMPA #imm20,Rdst | ||||||
| 0 | 0 | 0 | 0 | imm[19:16] | 1 | 0 | 1 | 0 | dst | imm[15:0] | ADDA #imm20,Rdst | ||||||
| 0 | 0 | 0 | 0 | imm[19:16] | 1 | 0 | 1 | 1 | dst | imm[15:0] | SUBA #imm20,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 1 | 1 | 0 | 0 | dst | — | MOVA Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 1 | 1 | 0 | 1 | dst | — | CMPA Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 1 | 1 | 1 | 0 | dst | — | ADDA Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 0 | src | 1 | 1 | 1 | 1 | dst | — | SUBA Rsrc,Rdst | ||||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | op. | mode | varies | CALLA | ||||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | RETI (Same as MSP430) |
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | As | register | CALLA source | |||||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | abs[19:16] | abs[15:0] | CALLA &abs20 | |||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | x[19:16] | x[15:0] | CALLA x(PC) | |||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | — | — | (reserved) | |||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | imm[19:16] | imm[15:0] | CALLA #imm20 | |||
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | — | — | (reserved) | |||||
| 0 | 0 | 0 | 1 | 0 | 1 | dir | W/A | n−1 | register | Push/pop n registers ending with specified | |||||||
| 0 | 0 | 0 | 1 | 0 | 1 | 0 | W/A | n−1 | src | — | PUSHM.x #n,Rsrc Push Rsrc, R(src−1), ... R(src−n+1) | ||||||
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | W/A | n−1 | dst−n+1 | — | POPM.x #n,Rdst Pop R(dst−n+1), R(dst−n+2), ... Rdst | ||||||
All other instructions can have a prefix word added which extends them to 20 bits. The prefix word contains an additional operand size bit, which is combined with the existing B/W bit to specify the operand size. There is one unused size combination; there are indications that this might be used in future for a 32-bit operand size.
The prefix word comes in two formats, and the choice between them depends on the instruction which follows.
If the instruction has any non-register operands, then the simple form is used, which provides 2 4-bit fields to extend any offset or immediate constant in the instruction stream.
If the instruction is register-to-register, a different extension word is used. This includes a "ZC" flag which suppresses carry-in (useful for instructions like DADD which always use the carry bit), and a repeat count. A 4-bit field in the extension word encodes either a repeat count (0–15 repetitions in addition to the initial execution), or a register number which contains a 4-bit repeat count.
| 15 | | 14 | | 13 | | 12 | 11 | | 10 | | 9 | | 8 | 7 | | 6 | | 5 | | 4 | 3 | | 2 | | 1 | | 0 | Instruction |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 | — | A/L | 0 | 0 | — | Extension word | ||||||
| 0 | 0 | 0 | 1 | 1 | src[19:16] | A/L | 0 | 0 | dst[19:16] | Memory operand extension | ||||||
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | ZC | 0 | A/L | 0 | 0 | n−1 | Register operand extension (immediate repeat count) | |||
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | ZC | 1 | A/L | 0 | 0 | Rn | Register operand extension (register repeat count) | |||
MSP430 address space
The general layout of the MSP430 address space is:0x0000–0x0007 : Processor special function registers (interrupt control registers)
0x0008–0x00FF : 8-bit peripherals. These must be accessed using 8-bit loads and stores.
0x0100–0x01FF : 16-bit peripherals. These must be accessed using 16-bit loads and stores.
0x0200–0x09FF : Up to 2048 bytes of RAM
Ram
-Animals:*Ram, an uncastrated male sheep*Ram cichlid, a species of freshwater fish endemic to Colombia and Venezuela-Military:*Battering ram*Ramming, a military tactic in which one vehicle runs into another...
.
0x0C00–0x0FFF : 1024 bytes of bootstrap loader ROM (flash ROM parts only).
0x1000–0x10FF : 256 bytes of data flash ROM (flash ROM parts only).
0x1100–0x38FF : Extended RAM on models with more than 2048 bytes of RAM. (0x1100–0x18FF is a copy of 0x0200–0x09FF)
0x1100–0xFFFF : Up to 60 kilobyte
Kilobyte
The kilobyte is a multiple of the unit byte for digital information. Although the prefix kilo- means 1000, the term kilobyte and symbol KB have historically been used to refer to either 1024 bytes or 1000 bytes, dependent upon context, in the fields of computer science and information...
s of program ROM. Smaller ROMs start at higher addresses. The last 16 or 32 bytes are interrupt vector
Interrupt vector
An interrupt vector is the memory address of an interrupt handler, or an index into an array called an interrupt vector table that contains the memory addresses of interrupt handlers...
s.
A few models include more than 2048 bytes of RAM; in that case RAM begins at 0x1100. The first 2048 bytes (0x1100–0x18FF) is mirrored at 0x0200–0x09FF for compatibility. Also, some recent models bend the 8-bit and 16-bit peripheral rules, allowing 16-bit access to peripherals in the 8-bit peripheral address range.
There is a new extended version of the architecture (called MSP430X) which allows a 20-bit address space
Address space
In computing, an address space defines a range of discrete addresses, each of which may correspond to a network host, peripheral device, disk sector, a memory cell or other logical or physical entity.- Overview :...
. It allows additional program ROM beginning at 0x10000.
The '5xx series has a greatly redesigned address space, with the first 4K devoted to peripherals, and up to 16K of RAM.
Peripherals
The MSP430 peripherals are generally easy to use, with (mostly) consistent addresses between models, and no write-only registers.General-purpose I/O ports 0–10
As is standard on microcontrollers, most pins connect to a more specialized peripheral, but if that peripheral is not needed, the pin may be used for general-purpose I/O. The pins are divided into 8-bit groups called "ports", each of which is controlled by a number of 8-bit registers. In some cases, the ports are arranged in pairs which can be accessed as 16-bit registers.The MSP430 family defines 11 I/O ports, P0 through P10, although no chip implements more than 10 of them. P0 is only implemented on the '3xx family. P7 through P10 are only implemented on the largest members (and highest pin count versions) of the '4xx and '2xx families. The newest '5xx and '6xx families has P1 through P11, and the control registers are reassigned to provide more port pairs.
Each port is controlled by the following registers. Ports which do not implement particular features (such as interrupt on state change) do not implement the corresponding registers.
PxIN : Port x input. This is a read-only register, and reflects the current state of the port's pins.
PxOUT : Port x output. The values written to this read/write register are driven out the corresponding pins when they are configured to output.
PxDIR : Port x data direction. Bits written as 1 configure the corresponding pin for output. Bits written as 0 configure the pin for input.
PxSEL : Port x function select. Bits written as 1 configure the corresponding pin for use by the specialized peripheral. Bits written as 0 configure the pin for general-purpose I/O. Port 0 ('3xx parts only) is not multiplexed with other peripherals and does not have a P0SEL register.
PxREN : Port x resistor enable ('2xx & '5xx only). Bits set in this register enable weak pull-up
Pull-up resistor
Pull-up resistors are used in electronic logic circuits to ensure that inputs to logic systems settle at expected logic levels if external devices are disconnected or high-impedance...
or pull-down resistors on the corresponding I/O pins even when they are configured as inputs. The direction of the pull is set by the bit written to the PxOUT register.
PxDS : Port x drive strength ('5xx only). Bits set in this register enable high-current outputs. This increases output power, but may cause EMI
Electromagnetic interference
Electromagnetic interference is disturbance that affects an electrical circuit due to either electromagnetic induction or electromagnetic radiation emitted from an external source. The disturbance may interrupt, obstruct, or otherwise degrade or limit the effective performance of the circuit...
.
Ports 0–2 can produce interrupts when inputs change. Additional registers configure this ability:
PxIES : Port x interrupt edge select. Selects the edge which will cause the PxIFG bit to be set. When the input bit changes from matching the PxIES state to not matching it (i.e. whenever a bit in PxIES XOR PxIN changes from clear to set), the corresponding PxIFG bit is set.
PxIE : Port x interrupt enable. When this bit and the corresponding PxIFG bit are both set, an interrupt is generated.
PxIFG : Port x interrupt flag. Set whenever the corresponding pin makes the state change requested by PxIES. Can be cleared only by software. (Can also be set by software.)
PxIV : Port x interrupt vector ('5xx only). This 16-bit register is a priority encoder
Priority encoder
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input bit...
which can be used to handle pin-change interrupts. If n is the lowest-numbered interrupt bit which is pending in PxIFG and enabled in PxIE, this register reads as 2n+2. If there is no such bit, it reads as 0. The scale factor of 2 allows direct use as an offset into a branch table
Branch table
In computer programming, a branch table is a term used to describe an efficient method of transferring program control to another part of a program using a table of branch instructions. It is a form of multiway branch...
. Reading this register also clears the reported PxIFG flag.
Some pins have special purposes either as inputs or outputs. (For example, timer pins can be configured as capture inputs or PWM outputs.) In this case, the PxDIR bit controls which of the two functions the pin performs when the PxSEL bit is set. If there is only one special function, then PxDIR is generally ignored.
The PxIN register is still readable if the PxSEL bit is set, but interrupt generation is disabled. If PxSEL is clear, the special function's input is frozen and disconnected from the external pin. Also, configuring a pin for general-purpose output does not disable interrupt generation.
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Intelligent Peripherals
Analog-to-Digital ConverterThe MSP430 line offers two types of Analog-to-Digital Conversion (ADC). 10- and 12-bit Successive Approximation converters, as well as a 16-bit Sigma-Delta converter. Data transfer controllers and a 16 word conversion-and-control buffer allow the MSP430 to convert and store samples without CPU intervention, minimizing power consumption.
Brown Out Reset
The Brown Out Reset circuitry detects low supply voltages and initiates a POR (Power On Reset) signal to reset the device. The MSP430's BOR circuit uses almost no power and is enabled at all times, including in all low power modes.
Comparator A, A+
The MSP430's comparator module provides precision slope Analog-to-Digital Conversions. Monitors external analog signals and provides voltage and resistor value measurement. Capable of selectable power modes.
Digital-to-Analog Converter
The MSP430's Digital-to-Analog Converter
Digital-to-analog converter
In electronics, a digital-to-analog converter is a device that converts a digital code to an analog signal . An analog-to-digital converter performs the reverse operation...
module features 8- and 12-bit modes and a programmable settling time for low power optimization. Internal or external reference selection is also possible.
Timers
The MSP 430 has 1 or 2 relatively flexible timers (5xxx series has 3). Each timer has 3 to 7 capture and compare registers that can each be observing the timer count and take a snap shot due to the change in an external signal or cause an external signal to change at a specified timer count. One of the timers can get its clock from an external signal. Timer clocks can not be gated or started and stopped by external signals. The ability to chain timers together to produce complex pulse sequences is limited. Interrupt generation is very flexible.
Direct Memory Access Controller
The MSP430's DMA allows data transfers from one address to another without CPU intervention, across the entire address range. Features up to three independent transfer channels.
Although the MSP430's DMA subsystem is very capable it has several flaws, the most significant of which is the lack of an external transfer strobe. Although a DMA transfer can be triggered externally, there is no external indication of completion of a transfer. Consequently DMA to and from external sources is limited to external trigger per byte transfers, rather than full blocks automatically via DMA. This can lead to significant complexity (as in requiring extensive hand tweaking of code) when implementing processor to processor or processor to USB communications. The reference cited uses an obscure timer mode to generate high speed strobes for DMA transfers. Unfortunately, the timers are not flexible enough to easily make up for the lack of an external DMA transfer strobe.
DMA operations that involve word transfers to byte locations cause truncation to 8 bits rather than conversion to two byte transfers. This makes DMA with A/D or D/A 16 bit values less useful than it could be (although it is possible to DMA these values through port A or B on some versions of the MSP 430 using an externally visible trigger per transfer such as a timer output).
ESP430 (integrated in FE42xx devices)
The ESP430CE module performs metering calculations independent of the CPU. Module has separate SD15, HW multiplier, and embedded processor engine.
LCD/LCD_A/LCD_B
The LCD/LCD_A controller directly drives LCD displays for up to 196 segments. Supports static, 2-mux, 3-mux, and 4-mux LCDs. LCD_A module has integrated charge pump for contrast control. LCD_B enables blinking of individual segments with separate blinking memory.
Op Amps
Feature single supply, low current operation with rail-to-rail outputs and programmable settling times. Software selectable configuration options: unity gain mode, comparator mode, inverting PGA, non-inverting PGA, differential and instrumentation amplifier.
Hardware multiplier
Some MSP430 models include a memory-mapped hardware multiplier peripheral which performs various 16×16+32→33-bit multiply-accumulate operations. Unusually for the MSP430, this peripheral does include an implicit 2-bit write-only register, which makes it effectively impossible to context switch
Context switch
A context switch is the computing process of storing and restoring the state of a CPU so that execution can be resumed from the same point at a later time. This enables multiple processes to share a single CPU. The context switch is an essential feature of a multitasking operating system...
.
The 8 registers used are:
| Address | Name | Function |
|---|---|---|
| 0x130 | MPY | Operand1 for unsigned multiply |
| 0x132 | MPYS | Operand1 for signed multiply |
| 0x134 | MAC | Operand1 for unsigned multiply-accumulate |
| 0x136 | MACS | Operand1 for signed multiply-accumulate |
| 0x138 | OP2 | Second operand for multiply operation |
| 0x13A | ResLo | Low word of multiply result |
| 0x13C | ResHi | High word of multiply result |
| 0x13E | SumExt | Carry out of multiply-accumulate |
The first operand is written to one of four 16-bit registers. The address written determines the operation performed. While the value written can be read back from any of the registers, the register number written to cannot be recovered.
If a multiply-accumulate operation is desired, the
ResLo and ResHi registers must also be initialized.Then, each time a write is performed to the
OP2 register, a multiply is performed and the result stored or added to the result registers. The SumExt register is a read-only register that contains the carry out of the addition (0 or 1) in case of an unsigned multiply), or the sign extension of the 32-bit sum (0 or -1) in case of a signed multiply. In the case of a signed multiply-accumulate, the SumExt value must be combined with the most significant bit of the prior SumHi contents to determine the true carry out result (-1, 0, or +1).The result is available after three clock cycles of delay, which is the time required to fetch a following instruction and a following index word. Thus, the delay is typically invisible. An explicit delay is only required if using an indirect addressing mode to fetch the result.
Development tools
Texas Instruments provides various hardware experimenter boards that support large (approximately two centimeters square) and small (approximately one millimeter square) MSP430 chips. TI also provides software development tools, both directly, and in conjunction with partners (see the full list of compilers, assemblers, and IDEs). One such toolchain is the IARIAR Systems
IAR Systems is a Swedish computer technology company working in the area of embedded system development tools. IAR Systems was founded in 1983, and is listed on NASDAQ OMX, Stockholm....
C/C++ compiler
Compiler
A compiler is a computer program that transforms source code written in a programming language into another computer language...
and Integrated development environment
Integrated development environment
An integrated development environment is a software application that provides comprehensive facilities to computer programmers for software development...
, or IDE. A Kickstart edition can be downloaded for free from TI or IAR; it is limited to 8 KB of C/C++ code in the compiler and debugger
Debugger
A debugger or debugging tool is a computer program that is used to test and debug other programs . The code to be examined might alternatively be running on an instruction set simulator , a technique that allows great power in its ability to halt when specific conditions are encountered but which...
(assembly language
Assembly language
An assembly language is a low-level programming language for computers, microprocessors, microcontrollers, and other programmable devices. It implements a symbolic representation of the machine codes and other constants needed to program a given CPU architecture...
programs of any size can be developed and debugged with this free toolchain).
TI also combines a version of its own compiler and tools with its Eclipse
Eclipse (software)
Eclipse is a multi-language software development environment comprising an integrated development environment and an extensible plug-in system...
-based Code Composer Studio
Code Composer Studio
Code Composer Studio is an integrated development environment for developing applications for Texas Instruments embedded processors. Texas Instruments embedded processors include DSPs, ARM based devices and other processors such as MSP430. Code Composer Studio includes a real time operating...
IDE ("CCS"). It sells full-featured versions, and offers a free version for download which has a code size limit of 16 KB. CCS supports in-circuit emulators, and includes a simulator and other tools; it can also work with other processors sold by TI.
The open source
Open source
The term open source describes practices in production and development that promote access to the end product's source materials. Some consider open source a philosophy, others consider it a pragmatic methodology...
community produces a freely available software development toolset based on the GNU toolset
GNU toolchain
The GNU toolchain is a blanket term for a collection of programming tools produced by the GNU Project. These tools form a toolchain used for developing applications and operating systems....
.
The GNU compiler is currently declined in three versions:
(MSPGCC)
(MSPGCC 4.x)
(MSPGCC Uniarch)
There is very early llvm-msp430 project, which may eventually provide better support for MSP430 in LLVM.
Other commercial development tool sets, which include editor, compiler, linker, assembler, debugger and in some cases code wizards, are available. VisSim
VisSim
VisSim is a visual block diagram language for simulation of dynamical systems and model based design of embedded systems. It is developed by Visual Solutions of Westford, Massachusetts....
, a block diagram
Block diagram
Block diagram is a diagram of a system, in which the principal parts or functions are represented by blocks connected by lines, that show the relationships of the blocks....
language for model based development, generates efficient fixed point
Fixed-point arithmetic
In computing, a fixed-point number representation is a real data type for a number that has a fixed number of digits after the radix point...
C-Code directly from the diagram. VisSim generated code for a closed loop
Feedback
Feedback describes the situation when output from an event or phenomenon in the past will influence an occurrence or occurrences of the same Feedback describes the situation when output from (or information about the result of) an event or phenomenon in the past will influence an occurrence or...
ADC+PWM based PID control on the F2013 compiles to less than 1 KB flash and 100 bytes RAM. VisSim has on-chip peripheral blocks for the entire MSP430 family I2C, ADC, SD16, PWM.
Development platforms
Since the MSP430 is targeted at customers interested in low power solutions to problems, TI has tackled the low-budget problem by offering a very small experimenter board, the eZ430-F2013, on a USB stick. This makes it easy for designers to choose the MSP430 chip for inexpensive development platforms that can be used with a computer. The eZ430-F2013 contains an MSP430F2013 microcontroller on a detachable prototyping board, and accompanying CD with development software. It is helpful for schools, hobbyists and garage inventors. It is also welcomed by engineers in large companies prototyping projects with capital budget problems.The MSP430F2013 and its siblings are set apart by the fact that (except for the MSP430G2 Value Line) it is the only MSP430 part that is available in a dual in-line package
Dual in-line package
In microelectronics, a dual in-line package is an electronic device package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board or inserted in a socket.A DIP is usually referred to as a DIPn, where n is...
(DIP). Other variants in this family are only available in various surface-mount packages. TI has gone to some trouble to support the eZ430 development platform by making the raw chips easily prototypable by hobbyists.
Texas Instruments
Texas Instruments
Texas Instruments Inc. , widely known as TI, is an American company based in Dallas, Texas, United States, which develops and commercializes semiconductor and computer technology...
released the MSP430 Launchpad in July 2010 at the price of $4.30 with free shipping. The MSP430 Launchpad has an onboard flash emulator, USB, 2 programmable LED
LEd
LEd is a TeX/LaTeX editing software working under Microsoft Windows. It is a freeware product....
s, and 1 programmable push button.
at the MSP430 Launchpad wiki.
Debugging interface
In common with other microcontroller vendors, TI has developed a two-wire debugging interface found on some of their MSP430 parts that can replace the larger JTAG interface. The eZ430 Development Tool contains a full USB-connected Flash Emulation Tool ("FET") for this new two-wire protocol, named "Spy-Bi-Wire" by TI. Spy-Bi-Wire was initially introduced on only the smallest devices in the 'F2xx family with limited number of I/O pins, such as the MSP430F20xx, MSP430F21x2, and MSP430F22x2. The support for Spy-Bi-Wire has been expanded with the introduction of the latest '5xx family, where all devices have support Spy-Bi-Wire interface in addition to JTAG.The advantage of the Spy-Bi-Wire protocol is that it uses only two communication lines, one of which is the dedicated _RESET line. The JTAG interface on the lower pin count MSP430 parts is multiplexed with general purpose I/O lines. This makes it relatively difficult to debug circuits built around the small, low-I/O-budget chips, since the full 4-pin JTAG hardware will conflict with anything else connected to those I/O lines. This problem is alleviated with the Spy-Bi-Wire-capable chips, which are still compatible with the normal JTAG interface for backwards compatibility with the old development tools.
JTAG debugging and flash programming tools based on OpenOCD and widely used in the ARM community are not available for the MSP430. Programming tools specially designed for the MSP430 are marginally less expensive than JTAG interfaces that use OpenOCD. However, should a project discover midstream that more MIPS, more memory, and more I/O peripherals are needed, those tools will not transfer to a processor from another vendor.
Community and information sites
- TI MSP430 Homepage
- TI MSP430 Community forum
- MSP430 Community sponsored by Texas Instruments
- msp430 Yahoo!group
- MSP430.info
- MSP430 English-Japanese forum
- 43oh.com – MSP430 News, Projects and Forums
- http://code.google.com/p/tinyos-msp430/tinyos-msp430 TinyOSTinyOSTinyOS is a free and open source component-based operating system and platform targeting wireless sensor networks . TinyOS is an embedded operating system written in the nesC programming language as a set of cooperating tasks and processes. It is intended to be incorporated into smartdust...
port]
Visual programming C code generators
Free Compiler and IDEs
- TI Code Composer Studio IDE, Microcontroller Core Edition (size limited to 16KB)
- IAR Embedded Workbench Kickstart IDE (size limited to 4/8/16KB - depends on device used)
- GCC toolchain for the MSP430 Microcontrollers
- GCC 4.x toolchain for the MSP430 Microcontrollers
- MSP430 Development System
- naken430asm Open-Source MSP430 assembler, disassembler, and simulator.
Most Popular Unrestricted IDEs and Compilers
- IAR Embedded Workbench for TI MSP430
- TI Code Composer Studio (CCS) Microcontroller or Platinum editions
- Rowley CrossWorks for MSP430 (only a 30-day evaluation period)
- GCC toolchain for the MSP430 Microcontrollers (Free C-compiler)
- MSP430 Development System
Miscellaneous IDEs
- AQ430 Development Tools for MSP430 Microcontrollers
- ImageCraft C Tools
- ForthInc Forth-Compiler
- MPE Forth-Compiler
- HI-TECH C for MSP430 (Dropped MSP430 Support in 2009)
List of debugging tools (not complete)
| Name | Manufacturer | Interface | Protocol(s) |
|---|---|---|---|
| MSP-FET430PIF | TI | Parallel-Port | JTAG |
| MSP-FET430UIF | TI | USB-Interface | JTAG, Spy-Bi-Wire |
| MSP-430 LaunchPad | TI | USB-Interface | Spy-Bi-Wire |
| eZ430-F2013 | TI | USB-Interface | Spy-Bi-Wire |
| eZ430-RF2500 | TI | USB-Interface | Spy-Bi-Wire |
| FETP | SoftBaugh | Parallel-Port | JTAG |
| USBP | SoftBaugh | USB-Interface | JTAG, Spy-Bi-Wire |
| MSP430-JTAG | Olimex | Parallel-Port | JTAG |
| MSP430-JTAG-ISO | Olimex | USB-Interface | JTAG, Spy-Bi-Wire |
| MSP430-JTAG-Tiny | Olimex | USB-Interface | JTAG, Spy-Bi-Wire |
| MSP430-JTAG-RF | Olimex | USB-Interface | JTAG, Spy-Bi-Wire |
| FlashPro-CC | Elprotronic | USB-Interface | JTAG, Spy-Bi-Wire, BSL |
| VisSim VisSim VisSim is a visual block diagram language for simulation of dynamical systems and model based design of embedded systems. It is developed by Visual Solutions of Westford, Massachusetts.... /ECD |
Visual Solutions | USB-Interface | JTAG, Spy-Bi-Wire |
| LA-3713 | Lauterbach | USB-Interface / Ethernet | JTAG, Spy-bi-Wire |
Other tools
- WSim - a software-driven emulator for full platform estimations and debug
- MSPSim - a Java based MSP430 emulator/simulator
- MSP430Static - a reverse engineering tool in Perl
- GoodFET - an open MSP430 JTAG debugger in C and Python
- mspdebug - an opensource MSP430 JTAG debugger
- Trace32 MSP430 SIM - Download area with MSP430 Instruction Set Simulator free for evaluation