StrongARM
Encyclopedia
The StrongARM is a family of microprocessor
s that implemented the ARM V4
instruction set architecture (ISA). It was developed by Digital Equipment Corporation
(DEC) and later sold to Intel, who continued to manufacture it before replacing it with the XScale
.
to create a faster ARM microprocessor. The StrongARM was designed to address the upper-end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support. Targets were devices such as newer personal digital assistant
s and set-top box
es.
Traditionally, the semiconductor
division of DEC was located in Massachusetts
. In order to gain access to the design talent in Silicon Valley
, DEC opened a design center in Palo Alto, California
. This design center was led by Dan Dobberpuhl and was the main design site for the StrongARM project. Another design site which worked on the project was in Austin, Texas
that was created by some ex-DEC designers returning from Apple Computer
and Motorola
. The project was set up in 1995, and quickly delivered their first design, the SA-110.
DEC agreed to sell StrongARM to Intel as part of a lawsuit settlement in 1997. Intel used the StrongARM to replace their ailing line of RISC processors, the i860
and i960
.
When the semiconductor division of DEC was sold to Intel, many engineers from the Palo Alto design group moved to SiByte, a start-up company designing MIPS
system-on-a-chip
s (SoCs) for the networking market. The Austin design group spun off to become Alchemy Semiconductor
, another start-up company designing MIPS SoCs for the hand-held market.
A new StrongARM core was developed by Intel and introduced in 2000 as the XScale
.
Risc PC
and Eidos Optima
video editing system. The SA-110's lead designers were Daniel W. Dobberpuhl
, Gregory W. Hoeppner, Liam Madden, and Richard T. Witek.
. It was a scalar
design that executed instructions in-order
with a five-stage classic RISC pipeline
. The microprocessor was partitioned into several blocks, the IBOX, EBOX, IMMU, DMMU, BIU, WB and PLL. The IBOX contained hardware that operated in the first two stages of the pipeline such as the program counter
. It fetched, decoded and issued instructions. Instruction fetch occurs during the first stage, decode and issue during the second. The IBOX decodes the more complex instructions in the ARM instruction set by translating them into sequences of simpler instructions. The IBOX also handled branch instructions. The SA-110 did not have branch prediction hardware, but had mechanisms for their speedy processing.
Execution starts at stage three. The hardware that operates during this stage is contained in the EBOX, which comprises the register file
, arithmetic logic unit
(ALU), barrel shifter
, multiplier
and condition code logic. The register file had three read ports and two write ports. The ALU and barrel shifter executed instructions in a single cycle. The multiplier is not pipelined and has a latency of multiple cycles.
The IMMU and DMMU are memory management unit
s for instructions and data, respectively. Each MMU contained a 32-entry fully associative translation lookaside buffer
(TLB) that can map 4 KB, 64 KB or 1 MB pages. The write buffer (WB) has eight 16-byte entries. It enables the pipelining of stores. The bus interface unit (BIU) provided the SA-110 with an external interface.
The PLL
generates the internal clock signal
from an external 3.68 MHz clock signal. It was not designed by DEC, but was contracted to the Centre Suisse d'Electronique et de Microtechnique (CSEM) located in Neuchâtel, Switzerland.
The instruction cache
and data cache each have a capacity of 16 KB and are 32-way set-associative and virtually addressed. The SA-110 was designed to be used with slow (and therefore low-cost) memory and therefore the high set associativity allows a higher hit rate than competing designs, and the use of virtual addresses allows memory to be simultaneously cached and uncached. The caches are responsible for most of the transistor count and they take up half the die area.
The SA-110 contained 2.5 million transistors and is 7.8 mm by 6.4 mm large (49.92 mm2). It was fabricated by DEC in its proprietary CMOS-6 process at its Fab 6 fab in Hudson, Massachusetts. CMOS-6 was DEC's sixth-generation complementary metal–oxide–semiconductor (CMOS) process. CMOS-6 has a 0.35 µm feature size, a 0.25 µm effective channel length but for use with the SA-110, only three levels of aluminium interconnect. It used a power supply with a variable voltage of 1.2 to 2.2 volt
s (V) to enable designs to find a balance between power consumption and performance (higher voltages enable higher clock rates). The SA-110 was packaged in a 144-pin thin quad flat pack (TQFP).
The extra features are integrated memory, PCMCIA, and color LCD controllers connected to an on-die system bus, and five serial I/O channels that are connected to a peripheral bus attached to the system bus. The memory controller supported FPM and EDO DRAM, SRAM, flash, and ROM. The PCMCIA controller supports two slots. The memory address and data bus is shared with the PCMCIA interface. Glue logic is required. The serial I/O channels implement a slave USB interface, a SDLC
, two UARTs, an IrDA
interface, a MCP, and a synchronous serial port
.
The SA-1100 had a companion chip, the SA-1101. It was introduced by Intel on 7 October 1998. The SA-1101 provided additional peripherals to complement those integrated on the SA-1100 such as a video output port, two PS/2
ports, a USB controller and a PCMCIA controller that replaces that on the SA-1100. Design of the device started by DEC, but was only partially complete when acquired by Intel, who had to finish the design. It was fabricated at DEC's former Hudson, Massachusetts
fabrication plant, which was also sold to Intel.
The SA-1100 contained 2.5 million transistors and measured 8.24 mm by 9.12 mm (75.15 mm2). It was fabricated in a 0.35 μm CMOS process with three levels of aluminium interconnect and was packaged in a 208-pin TQFP.
. Its companion chip, which provided additional support for peripherals, was the SA-1111. The SA-1110 was packaged in a 256-pin micro ball grid array
. It was used in mobile phones, personal data assistants (PDAs) such as the Compaq (later HP) iPAQ
and HP Jornada, the Sharp SL-5x00 Linux Based Platforms and the Simputer
.
es. It was designed and manufactured in low volumes by DEC but was never put into production by Intel. The SA-1500 was available at 200 to 300 MHz. The SA-1500 featured an enhanced SA-110 core, an on-chip coprocessor
called the Attached Media Processor (AMP), and an on-chip SDRAM and I/O bus controller. The SDRAM controller supported 100 MHz SDRAM, and the I/O controller implemented a 32-bit I/O bus that may run at frequencies up to 50 MHz for connecting to peripherals and the SA-1501 companion chip.
The AMP implemented a long instruction word instruction set containing instructions designed for multimedia, such as integer and floating-point multiply–accumulate and SIMD
arithmetic. Each long instruction word is 64 bits wide and specifies an arithmetic operation and a branch or a load/store. Instructions operate on operands from a 64-entry 36-bit register file, and on a set of control registers. The AMP communicates with the SA-110 core via an on-chip bus and it shares the data cache with the SA-110. The AMP contained an ALU with a shifter, a branch unit, a load/store unit, a multiply–accumulate unit, and a single-precision floating-point unit. The AMP supported user-defined instructions via a 512-entry writable control store.
The SA-1501 companion chip provided additional video and audio processing capabilities and various I/O functions such as PS/2 ports, a parallel port, and interfaces for various peripherals.
The SA-1500 contains 3.3 million transistors and measures 60 mm2. It was fabricated in a 0.28 µm CMOS process. It used a 1.5 to 2.0 V internal power supply and 3.3 V I/O, consuming less than 0.5 W at 100 MHz and 2.5 W at 300 MHz. It was packaged in a 240-pin metal quad flat package
or a 256-ball plastic ball grid array.
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
s that implemented the ARM V4
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
instruction set architecture (ISA). It was developed by Digital Equipment Corporation
Digital Equipment Corporation
Digital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
(DEC) and later sold to Intel, who continued to manufacture it before replacing it with the XScale
XScale
The XScale, a microprocessor core, is Intel's and Marvell's implementation of the ARMv5 architecture, and consists of several distinct families: IXP, IXC, IOP, PXA and CE . Intel sold the PXA family to Marvell Technology Group in June 2006....
.
History
The StrongARM was a collaborative project between DEC and Advanced RISC MachinesARM Holdings
ARM Holdings plc is a British multinational semiconductor and software company headquartered in Cambridge. Its largest business is in processors, although it also designs, licenses and sells software development tools under the RealView and KEIL brands, systems and platforms, system-on-a-chip...
to create a faster ARM microprocessor. The StrongARM was designed to address the upper-end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support. Targets were devices such as newer personal digital assistant
Personal digital assistant
A personal digital assistant , also known as a palmtop computer, or personal data assistant, is a mobile device that functions as a personal information manager. Current PDAs often have the ability to connect to the Internet...
s and set-top box
Set-top box
A set-top box or set-top unit is an information appliance device that generally contains a tuner and connects to a television set and an external source of signal, turning the signal into content which is then displayed on the television screen or other display device.-History:Before the...
es.
Traditionally, the semiconductor
Semiconductor
A semiconductor is a material with electrical conductivity due to electron flow intermediate in magnitude between that of a conductor and an insulator. This means a conductivity roughly in the range of 103 to 10−8 siemens per centimeter...
division of DEC was located in Massachusetts
Massachusetts
The Commonwealth of Massachusetts is a state in the New England region of the northeastern United States of America. It is bordered by Rhode Island and Connecticut to the south, New York to the west, and Vermont and New Hampshire to the north; at its east lies the Atlantic Ocean. As of the 2010...
. In order to gain access to the design talent in Silicon Valley
Silicon Valley
Silicon Valley is a term which refers to the southern part of the San Francisco Bay Area in Northern California in the United States. The region is home to many of the world's largest technology corporations...
, DEC opened a design center in Palo Alto, California
Palo Alto, California
Palo Alto is a California charter city located in the northwest corner of Santa Clara County, in the San Francisco Bay Area of California, United States. The city shares its borders with East Palo Alto, Mountain View, Los Altos, Los Altos Hills, Stanford, Portola Valley, and Menlo Park. It is...
. This design center was led by Dan Dobberpuhl and was the main design site for the StrongARM project. Another design site which worked on the project was in Austin, Texas
Austin, Texas
Austin is the capital city of the U.S. state of :Texas and the seat of Travis County. Located in Central Texas on the eastern edge of the American Southwest, it is the fourth-largest city in Texas and the 14th most populous city in the United States. It was the third-fastest-growing large city in...
that was created by some ex-DEC designers returning from Apple Computer
Apple Computer
Apple Inc. is an American multinational corporation that designs and markets consumer electronics, computer software, and personal computers. The company's best-known hardware products include the Macintosh line of computers, the iPod, the iPhone and the iPad...
and Motorola
Motorola
Motorola, Inc. was an American multinational telecommunications company based in Schaumburg, Illinois, which was eventually divided into two independent public companies, Motorola Mobility and Motorola Solutions on January 4, 2011, after losing $4.3 billion from 2007 to 2009...
. The project was set up in 1995, and quickly delivered their first design, the SA-110.
DEC agreed to sell StrongARM to Intel as part of a lawsuit settlement in 1997. Intel used the StrongARM to replace their ailing line of RISC processors, the i860
Intel i860
The Intel i860 was a RISC microprocessor from Intel, first released in 1989. The i860 was one of Intel's first attempts at an entirely new, high-end instruction set since the failed Intel i432 from the 1980s...
and i960
Intel i960
Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller, becoming a best-selling CPU in that field, along with the competing AMD 29000...
.
When the semiconductor division of DEC was sold to Intel, many engineers from the Palo Alto design group moved to SiByte, a start-up company designing MIPS
MIPS architecture
MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...
system-on-a-chip
System-on-a-chip
A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
s (SoCs) for the networking market. The Austin design group spun off to become Alchemy Semiconductor
Alchemy (processor)
The Alchemy microprocessor is a low power processor family that uses MIPS architecture. The Alchemy family was used by AMD, Raza Microelectronics and Sun Microsystems in its embedded products such as Network processors....
, another start-up company designing MIPS SoCs for the hand-held market.
A new StrongARM core was developed by Intel and introduced in 2000 as the XScale
XScale
The XScale, a microprocessor core, is Intel's and Marvell's implementation of the ARMv5 architecture, and consists of several distinct families: IXP, IXC, IOP, PXA and CE . Intel sold the PXA family to Marvell Technology Group in June 2006....
.
SA-110
The SA-110 was the first microprocessor in the StrongARM family. The first versions, operating at 100, 160, and 200 MHz, were announced on 5 February 1996. When announced, samples of these versions were available, with volume production slated for mid-1996. Faster 166 and 233 MHz versions were announced on 12 September 1996. Samples of these versions were available at announcement, with volume production slated for December 1996. Throughout 1996, the SA-110 was the highest performing microprocessor for portable devices. The SA-110's first design win was the Apple MessagePad 2000. It was also used in a number of products including the Acorn ComputersAcorn Computers
Acorn Computers Ltd. was a British computer company established in Cambridge, England, in 1978. The company produced a number of computers which were especially popular in the UK. These included the Acorn Electron, the BBC Micro, and the Acorn Archimedes...
Risc PC
Risc PC
The RiscPC was Acorn Computers's next generation RISC OS/Acorn RISC Machine computer, launched on 15 April 1994, which superseded the Acorn Archimedes. The Acorn PC card and software allows PC compatible software to be run....
and Eidos Optima
Eidos Interactive
Eidos Interactive Ltd. is a British video game publisher and is a label of Square Enix Europe. As an independent company Eidos plc was headquartered in the Wimbledon Bridge House in Wimbledon, London Borough of Merton....
video editing system. The SA-110's lead designers were Daniel W. Dobberpuhl
Daniel W. Dobberpuhl
Daniel "Dan" W. Dobberpuhl is an electrical engineer in the United States who led several teams of microprocessor designers.- Background :...
, Gregory W. Hoeppner, Liam Madden, and Richard T. Witek.
Description
The SA-110 had a simple microarchitectureMicroarchitecture
In computer engineering, microarchitecture , also called computer organization, is the way a given instruction set architecture is implemented on a processor. A given ISA may be implemented with different microarchitectures. Implementations might vary due to different goals of a given design or...
. It was a scalar
Scalar processor
Scalar processors represent the simplest class of computer processors. A scalar processor processes one datum at a time . , a scalar processor is classified as a SISD processor .In a vector processor, by contrast, a single instruction operates simultaneously on multiple data items...
design that executed instructions in-order
Out-of-order execution
In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...
with a five-stage classic RISC pipeline
Classic RISC pipeline
In the history of computer hardware, some early reduced instruction set computer central processing units used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000, and later DLX....
. The microprocessor was partitioned into several blocks, the IBOX, EBOX, IMMU, DMMU, BIU, WB and PLL. The IBOX contained hardware that operated in the first two stages of the pipeline such as the program counter
Program counter
The program counter , commonly called the instruction pointer in Intel x86 microprocessors, and sometimes called the instruction address register, or just part of the instruction sequencer in some computers, is a processor register that indicates where the computer is in its instruction sequence...
. It fetched, decoded and issued instructions. Instruction fetch occurs during the first stage, decode and issue during the second. The IBOX decodes the more complex instructions in the ARM instruction set by translating them into sequences of simpler instructions. The IBOX also handled branch instructions. The SA-110 did not have branch prediction hardware, but had mechanisms for their speedy processing.
Execution starts at stage three. The hardware that operates during this stage is contained in the EBOX, which comprises the register file
Register file
A register file is an array of processor registers in a central processing unit . Modern integrated circuit-based register files are usually implemented by way of fast static RAMs with multiple ports...
, arithmetic logic unit
Arithmetic logic unit
In computing, an arithmetic logic unit is a digital circuit that performs arithmetic and logical operations.The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers...
(ALU), barrel shifter
Barrel shifter
A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers , and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift...
, multiplier
Binary multiplier
A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders....
and condition code logic. The register file had three read ports and two write ports. The ALU and barrel shifter executed instructions in a single cycle. The multiplier is not pipelined and has a latency of multiple cycles.
The IMMU and DMMU are memory management unit
Memory management unit
A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...
s for instructions and data, respectively. Each MMU contained a 32-entry fully associative translation lookaside buffer
Translation Lookaside Buffer
A translation lookaside buffer is a CPU cache that memory management hardware uses to improve virtual address translation speed. All current desktop and server processors use a TLB to map virtual and physical address spaces, and it is ubiquitous in any hardware which utilizes virtual memory.The...
(TLB) that can map 4 KB, 64 KB or 1 MB pages. The write buffer (WB) has eight 16-byte entries. It enables the pipelining of stores. The bus interface unit (BIU) provided the SA-110 with an external interface.
The PLL
Phase-locked loop
A phase-locked loop or phase lock loop is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector...
generates the internal clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
from an external 3.68 MHz clock signal. It was not designed by DEC, but was contracted to the Centre Suisse d'Electronique et de Microtechnique (CSEM) located in Neuchâtel, Switzerland.
The instruction cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
and data cache each have a capacity of 16 KB and are 32-way set-associative and virtually addressed. The SA-110 was designed to be used with slow (and therefore low-cost) memory and therefore the high set associativity allows a higher hit rate than competing designs, and the use of virtual addresses allows memory to be simultaneously cached and uncached. The caches are responsible for most of the transistor count and they take up half the die area.
The SA-110 contained 2.5 million transistors and is 7.8 mm by 6.4 mm large (49.92 mm2). It was fabricated by DEC in its proprietary CMOS-6 process at its Fab 6 fab in Hudson, Massachusetts. CMOS-6 was DEC's sixth-generation complementary metal–oxide–semiconductor (CMOS) process. CMOS-6 has a 0.35 µm feature size, a 0.25 µm effective channel length but for use with the SA-110, only three levels of aluminium interconnect. It used a power supply with a variable voltage of 1.2 to 2.2 volt
Volt
The volt is the SI derived unit for electric potential, electric potential difference, and electromotive force. The volt is named in honor of the Italian physicist Alessandro Volta , who invented the voltaic pile, possibly the first chemical battery.- Definition :A single volt is defined as the...
s (V) to enable designs to find a balance between power consumption and performance (higher voltages enable higher clock rates). The SA-110 was packaged in a 144-pin thin quad flat pack (TQFP).
SA-1100
The SA-1100 was a derivative of the SA-110 developed by DEC. Announced in 1997, the SA-1100 was targeted for portable applications such as PDAs and differs from the SA-110 by providing a number of features that are desirable for such applications. To accommodate these features, the data cache was reduced in size to 8 KB.The extra features are integrated memory, PCMCIA, and color LCD controllers connected to an on-die system bus, and five serial I/O channels that are connected to a peripheral bus attached to the system bus. The memory controller supported FPM and EDO DRAM, SRAM, flash, and ROM. The PCMCIA controller supports two slots. The memory address and data bus is shared with the PCMCIA interface. Glue logic is required. The serial I/O channels implement a slave USB interface, a SDLC
Synchronous Data Link Control
Synchronous Data Link Control is a computer communications protocol. It is the layer 2 protocol for IBM's Systems Network Architecture . SDLC supports multipoint links as well as error correction. It also runs under the assumption that an SNA header is present after the SDLC header...
, two UARTs, an IrDA
IRDA
IRDA may refer to:* Infrared Data Association, in information and communications technology , a standard for communication between devices over short distances using infrared signals...
interface, a MCP, and a synchronous serial port
Synchronous Serial Port
A Synchronous Serial Port is a controller that supports the Serial Peripheral Interface , 4-wire Synchronous Serial Interface , and Microwire serial buses. A SSP uses a master-slave paradigm to communicate across its connected bus....
.
The SA-1100 had a companion chip, the SA-1101. It was introduced by Intel on 7 October 1998. The SA-1101 provided additional peripherals to complement those integrated on the SA-1100 such as a video output port, two PS/2
PS/2 connector
The PS/2 connector is a 6-pin Mini-DIN connector used for connecting some keyboards and mice to a PC compatible computer system. Its name comes from the IBM Personal System/2 series of personal computers, with which it was introduced in 1987...
ports, a USB controller and a PCMCIA controller that replaces that on the SA-1100. Design of the device started by DEC, but was only partially complete when acquired by Intel, who had to finish the design. It was fabricated at DEC's former Hudson, Massachusetts
Hudson, Massachusetts
Hudson is a town in Middlesex County, Massachusetts, United States. The population was 19,063 at the 2010 census. The town is located in central Massachusetts, about a 40-minute drive, or about , west of Boston, and about a 20-minute drive, or about , northeast of Worcester.Before its...
fabrication plant, which was also sold to Intel.
The SA-1100 contained 2.5 million transistors and measured 8.24 mm by 9.12 mm (75.15 mm2). It was fabricated in a 0.35 μm CMOS process with three levels of aluminium interconnect and was packaged in a 208-pin TQFP.
SA-1110
The SA-1110 was a derivative of the SA-110 developed by Intel. It was announced on 31 March 1999, positioned as an alternative to the SA-1100. At announcement, samples were set for June 1999 and volume later that year. Intel discontinued the SA-1110 in early 2003. The SA-1110 was available in 133 or 206 MHz versions. It differed from the SA-1100 by featuring support for 66 MHz (133 MHz version only) or 103 MHz (206 MHz version only) SDRAMSDRAM
Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
. Its companion chip, which provided additional support for peripherals, was the SA-1111. The SA-1110 was packaged in a 256-pin micro ball grid array
Ball grid array
A ball grid array is a type of surface-mount packaging used for integrated circuits.- Description :The BGA is descended from the pin grid array , which is a package with one face covered with pins in a grid pattern. These pins conduct electrical signals from the integrated circuit to the printed...
. It was used in mobile phones, personal data assistants (PDAs) such as the Compaq (later HP) iPAQ
IPAQ
iPAQ presently refers to a Pocket PC and personal digital assistant first unveiled by Compaq in April 2000; the name was borrowed from Compaq's earlier iPAQ Desktop Personal Computers. Since Hewlett-Packard's acquisition of Compaq, the product has been marketed by HP. The devices use a Windows...
and HP Jornada, the Sharp SL-5x00 Linux Based Platforms and the Simputer
Simputer
The Simputer is a self-contained, open hardware Linux-based handheld computer, first released in 2002. Developed in, and primarily distributed within India, the product was envisioned as a low-cost alternative to personal computers...
.
SA-1500
The SA-1500 was a derivative of the SA-110 developed by DEC initially targeted for set-top boxSet-top box
A set-top box or set-top unit is an information appliance device that generally contains a tuner and connects to a television set and an external source of signal, turning the signal into content which is then displayed on the television screen or other display device.-History:Before the...
es. It was designed and manufactured in low volumes by DEC but was never put into production by Intel. The SA-1500 was available at 200 to 300 MHz. The SA-1500 featured an enhanced SA-110 core, an on-chip coprocessor
Coprocessor
A coprocessor is a computer processor used to supplement the functions of the primary processor . Operations performed by the coprocessor may be floating point arithmetic, graphics, signal processing, string processing, or encryption. By offloading processor-intensive tasks from the main processor,...
called the Attached Media Processor (AMP), and an on-chip SDRAM and I/O bus controller. The SDRAM controller supported 100 MHz SDRAM, and the I/O controller implemented a 32-bit I/O bus that may run at frequencies up to 50 MHz for connecting to peripherals and the SA-1501 companion chip.
The AMP implemented a long instruction word instruction set containing instructions designed for multimedia, such as integer and floating-point multiply–accumulate and SIMD
SIMD
Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...
arithmetic. Each long instruction word is 64 bits wide and specifies an arithmetic operation and a branch or a load/store. Instructions operate on operands from a 64-entry 36-bit register file, and on a set of control registers. The AMP communicates with the SA-110 core via an on-chip bus and it shares the data cache with the SA-110. The AMP contained an ALU with a shifter, a branch unit, a load/store unit, a multiply–accumulate unit, and a single-precision floating-point unit. The AMP supported user-defined instructions via a 512-entry writable control store.
The SA-1501 companion chip provided additional video and audio processing capabilities and various I/O functions such as PS/2 ports, a parallel port, and interfaces for various peripherals.
The SA-1500 contains 3.3 million transistors and measures 60 mm2. It was fabricated in a 0.28 µm CMOS process. It used a 1.5 to 2.0 V internal power supply and 3.3 V I/O, consuming less than 0.5 W at 100 MHz and 2.5 W at 300 MHz. It was packaged in a 240-pin metal quad flat package
QFP
A QFP or Quad Flat Package is a surface mount integrated circuit package with leads extending from each of the four sides. Socketing such packages is rare and hole mounting is not possible. Versions ranging from 32 to 304 pins with a pitch ranging from 0.4 to 1.0 mm are common...
or a 256-ball plastic ball grid array.
Further reading
- "StrongARM-1500 Grapples With MPEG-2". (8 December 1997). Microprocessor Report.
- Halfhill, Tom R. (19 April 1999). "Intel Flexes StrongArm With New Chips". Microprocessor Report.
- Litch, Tim; Slaton, Jeff (March/April) 1998). "StrongARMing Portable Communications". IEEE MicroIEEE MicroIEEE Micro is a broad-based practitioner-oriented magazine of the IEEE Computer Society targeting small system and semiconductor chip professionals, including electronic engineers, designers, architects, developers, process improvement experts, testers, quality engineers, and project managers...
. pp. 48–55. - Santhanam, S. et al. (November 1998). "A low-cost, 300-MHz, RISC CPU with attached media processor". IEEE Journal of Solid-State Circuits, vol. 33, no. 11. pp. 1829–1839.
- Turley, Jim (13 November 1995). "StrongArm Punches Up ARM Performance". Microprocessor Report.
- Turley, Jim (15 September 1997). "SA-1100 Puts PDA on a Chip". Microprocessor Report.
- Witek, Rich; Montanaro, James (1996). "StrongARM: A high-performance ARM processor". Proceedings of COMPCON '96, pp. 188–191.