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PIC is a family of Harvard architecture microcontrollers made by Microchip Technology, derived from the PIC1640 originally developed by General Instrument's Microelectronics Division. The name PIC initially referred to "Peripheral Interface Controller".
PICs are popular with developers and hobbyists alike due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, and serial programming (and re-programming with flash memory) capability.
Microchip announced on February 2008 the shipment of its six billionth PIC processor.
PIC architecture is distinctively minimalist.
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Encyclopedia
PIC is a family of Harvard architecture microcontrollers made by Microchip Technology, derived from the PIC1640 originally developed by General Instrument's Microelectronics Division. The name PIC initially referred to "Peripheral Interface Controller".
PICs are popular with developers and hobbyists alike due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, and serial programming (and re-programming with flash memory) capability.
Microchip announced on February 2008 the shipment of its six billionth PIC processor.
Core architecture
The PIC architecture is distinctively minimalist. It is characterized by the following features:
- Separate code and data spaces (Harvard architecture)
- A small number of fixed length instructions
- Most instructions are single cycle execution (4 clock cycles), with single delay cycles upon branches and skips
- A single accumulator (W), the use of which (as source operand) is implied (i.e. is not encoded in the opcode)
- All RAM locations function as registers as both source and/or destination of math and other functions.
- A hardware stack for storing return addresses
- A fairly small amount of addressable data space (typically 256 bytes), extended through banking
- Data space mapped CPU, port, and peripheral registers
- The program counter is also mapped into the data space and writable (this is used to implement indirect jumps).
Unlike most other CPUs, there is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.
Data space (RAM)
PICs have a set of registers that function as general purpose RAM. Special purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend the addressing to additional memory. Later series of devices feature move instructions which can cover the whole addressable space, independent of the selected bank. In earlier devices (i.e., the baseline and mid-range cores), any register move had to be achieved via the accumulator.
To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF) are used: A register number is written to the FSR, after which reads from or writes to INDF will actually be to or from the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer.
External data memory is not directly addressable except in some high pin count PIC18 devices.
Code space
All PICs feature Harvard architecture, so the code space and the data space are separate. PIC code space is generally implemented as EPROM, ROM, or flash ROM.
In general, external code memory is not directly due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices.
Word size
The word size of PICs can be a source of confusion. All PICs handle (and address) data in 8-bit chunks, so they should be called 8-bit microcontrollers. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline and mid-range families have program memory addressable in the same wordsize as the instruction width, ie. 12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs from the instruction width of 16 bits.
In order to be clear, the program memory capacity is usually stated in number of (single word) instructions, rather than in bytes.
Stacks
PICs have a hardware call stack, which is used to save return addresses. The hardware stack is not software accessible on earlier devices, but this changed with the 18 series devices.
Hardware support for a general purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high level language compilers.
Instruction set
A PIC's instructions vary in from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a register, as well as for conditional execution, and program branching.
Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W; writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the "high end" cores.
PIC cores have skip instructions which are used for conditional execution and branching. The skip instructions are: 'skip if bit set', and, 'skip if bit not set'. Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction.
The PIC architecture has no (or very meager) hardware support for automatically saving processor state when servicing interrupts. The 18 series improved this situation by implementing shadow registers which save several important registers during an interrupt.
In general, PIC instructions fall into 5 classes:
- Operation on W with 8-bit immediate ("literal") operand. E.g.
movlw (move literal to W), andlw (AND literal with W). One instruction peculiar to the PIC is retlw, load immediate into W and return, which is used with computed branches to produce lookup tables. - Operation with W and indexed register. The result can be written to either the W register (e.g.
addwf reg,w). or the selected register (e.g. addwf reg,f). - Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible.
- Control transfers. Other than the skip instructions previously mentioned, there are only two:
goto and call. - A few miscellaneous zero-operand instructions, such as return from subroutine, and
sleep to enter low-power mode.
Interrupt Latency
A very useful and unique property of PICs is that their interrupt latency is constant (it's also low: 3 instruction cycles). The delay is constant even though instructions can take one or two instruction cycles: a dead cycle is optionally inserted into the interrupt response sequence to make this true. External interrupts have to be synchronized with the four clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized.
The constant interrupt latency allows PICs to achieve interrupt driven low jitter timing sequences. An example of this is a video sync pulse generator. Other microcontrollers can do this in some cases, but it's awkward. The non-interrupt code has to anticipate the interrupt and enter into a sleep state before it arrives. On PICs, there is no need for this.
The three-cycle latency is increased in practice because the PIC does not store its registers when entering the interrupt routine. Typically, 4 instructions are needed to store the W-register, the status register and switch to a specific bank before starting the actual interrupt processing.
Limitations
The PIC architectures have several limitations:
- Only a single accumulator
- A small instruction set
- Operations and registers are not orthogonal; some instructions can address RAM and/or immediate constants, while others can only use the accumulator
- Memory must be directly referenced in arithmetic and logic operations, although indirect addressing is available via 2 additional registers
- Register-bank switching is required to access the entire RAM of many devices, making position-independent code complex and inefficient
- Conditional skip instructions are used instead of conditional branch instructions used by most other architectures
The following limitations have been addressed in the PIC18, but still apply to earlier cores:
- Indexed addressing mode is very rudimentary
- Stack:
- The hardware call stack is so small that program structure must often be flattened
- The hardware call stack is not addressable, so pre-emptive task switching cannot be implemented
- Software-implemented stacks are not efficient, so it is difficult to generate reentrant code and support local variables
- Program memory is not directly addressable, and thus space-inefficient and/or time-consuming to access. (This is true of most Harvard architecture microcontrollers.)
With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example, on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2KB. For computed GOTOs, where you add to PCL, the page size is 256 bytes. In both cases, the upper address bits are provided by the PCLATH register. This register must be changed every time control transfers between pages. PCLATH must also be preserved by any interrupt handler.
Compiler development
These properties have made it difficult to develop compilers that target PIC microcontrollers. While several commercial compilers are available, in 2008, Microchip finally released their C compilers, C18, and C30 for their line of 18f 24f and 30/33f processors. By contrast, Atmel's AVR microcontrollers—which are competitive with PIC in terms of hardware capabilities and price, but feature a RISC instruction set—have long been supported by the GNU C Compiler.
Also, because of these properties, PIC assembly language code can be difficult to comprehend. Judicious use of simple macros can make PIC assembly language much more palatable, but at the cost of a reduction in performance. For example, the original Parallax PIC assembler "pasm" has macros which hide W and make the PIC look like a two-address machine. It has macro instructions like "mov b,a" (move the data from address a to address b) and "add b,a" (add data from address a to data in address b). It also hides the skip instructions by providing three operand branch macro instructions such as "cjne a,b,dest" (compare a with b and jump to dest if they are not equal).
Family Core Architectural Differences
Baseline Core Devices
These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.
Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 16–31; registers 0–15 are global and not affected by the bank select bits.
The ROM address space is 512 words (12 bits each), which may be extended to 2048 words by banking. CALL and GOTO instructions specify the low 9 bits of the new code location; additional high-order bits are taken from the staus register. Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each 512-word page.
The instruction set is as follows. Register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". The "d" bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f.
12-bit PIC instruction set| Opcode (binary) | Mnemonic | Description | 0000 0000 0000 | NOP | No operation | 0000 0000 0010 | OPTION | Load OPTION register with contents of W | 0000 0000 0011 | SLEEP | Go into standby mode | 0000 0000 0100 | CLRWDT | Reset watchdog timer | 0000 0000 01ff | TRIS f | Move W to port control register (f=1..3) | | | 0000 001 fffff | MOVWF f | Move W to f | 0000 010 xxxxx | CLRW | Clear W to 0 (a.k.a CLR x,W) | 0000 011 fffff | CLRF f | Clear f to 0 (a.k.a. CLR f,F) | 0000 10d fffff | SUBWF f,d | Subtract W from f (d = f - W) | 0000 11d fffff | DECF f,d | Decrement f (d = f - 1) | 0001 00d fffff | IORWF f,d | Inclusive OR W with F (d = f OR W) | 0001 01d fffff | ANDWF f,d | AND W with F (d = f AND W) | 0001 10d fffff | XORWF f,d | Exclusive OR W with F (d = f XOR W) | 0001 11d fffff | ADDWF f,d | Add W with F (d = f + W) | 0010 00d fffff | MOVF f,d | Move F (d = f) | 0010 01d fffff | COMF f,d | Complement f (d = NOT f) | 0010 10d fffff | INCF f,d | Increment f (d = f + 1) | 0010 11d fffff | DECFSZ f,d | Decrement f (d = f - 1) and skip if zero | 0011 00d fffff | RRF f,d | Rotate right F (rotate right through carry) | 0011 01d fffff | RLF f,d | Rotate left F (rotate left through carry) | 0011 10d fffff | SWAPF f,d | Swap 4-bit halves of f (d = f<<4 | f>>4) | 0011 11d fffff | INCFSZ f,d | Increment f (d = f + 1) and skip if zero | | | 0100 bbb fffff | BCF f,b | Bit clear f (Clear bit b of f) | 0101 bbb fffff | BSF f,b | Bit set f (Set bit b of f) | 0110 bbb fffff | BTFSC f,b | Bit test f, skip if clear (Test bit b of f) | 0111 bbb fffff | BTFSS f,b | Bit test f, skip if set (Test bit b of f) | | | 1000 kkkkkkkk | RETLW k | Set W to k and return | 1001 kkkkkkkk | CALL k | Save return address, load PC with k | 101 kkkkkkkkk | GOTO k | Jump to address k (9 bits!) | 1100 kkkkkkkk | MOVLW k | Move literal to W (W = k) | 1101 kkkkkkkk | IORLW k | Inclusive or literal with W (W = k OR W) | 1110 kkkkkkkk | ANDLW k | AND literal with W (W = k AND W) | 1111 kkkkkkkk | XORLW k | Exclusive or literal with W (W = k XOR W) |
Mid-Range Core Devices
These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the increased opcode width allows 128 registers and 2048 words of code to be directly addressed. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.
The first 32 bytes of the register space are allocated to special-purpose registers; the remaining 96 bytes are used for general-purpose RAM. If banked RAM is used, the high 16 registers (0x70–0x7F) are global, as are a few of the most important special-purpose registers, including the STATUS register which holds the RAM bank select bits. (The other global registers are FSR and INDF, the low 8 bits of the program counter PCL, the PC high preload register PCLATH, and the master interrupt control register INTCON.)
The PCLATH register supplies high-order instruction address bits when the 8 bits supplied by a write to the PCL register, or the 11 bits supplied by a GOTO or CALL instruction, is not sufficient to address the available ROM space.
14-bit PIC instruction set| Opcode (binary) | Mnemonic | Description | 00 0000 0000 0000 | NOP | No operation | 00 0000 0000 1000 | RETURN | Return from subroutine, W unchanged | 00 0000 0000 1001 | RETFIE | Return from interrupt | 00 0000 0110 0010 | OPTION | Write W to OPTION register | 00 0000 0110 0011 | SLEEP | Go into standby mode | 00 0000 0110 0100 | CLRWDT | Reset watchdog timer | 00 0000 0110 01ff | TRIS f | Write W to tristate register f | | | 00 0000 1 fffffff | MOVWF f | Move W to f | 00 0001 0 xxxxxxx | CLRW | Clear W to 0 (W = 0) | 00 0001 1 fffffff | CLRF f | Clear f to 0 (f = 0) | 00 0010 d fffffff | SUBWF f,d | Subtract W from f (d = f - W) | 00 0011 d fffffff | DECF f,d | Decrement f (d = f - 1) | 00 0100 d fffffff | IORWF f,d | Inclusive OR W with F (d = f OR W) | 00 0101 d fffffff | ANDWF f,d | AND W with F (d = f AND W) | 00 0110 d fffffff | XORWF f,d | Exclusive OR W with F (d = f XOR W) | 00 0111 d fffffff | ADDWF f,d | Add W with F (d = f + W) | 00 1000 d fffffff | MOVF f,d | Move F (d = f) | 00 1001 d fffffff | COMF f,d | Complement f (d = NOT f) | 00 1010 d fffffff | INCF f,d | Increment f (d = f + 1) | 00 1011 d fffffff | DECFSZ f,d | Decrement f (d = f - 1) and skip if zero | 00 1100 d fffffff | RRF f,d | Rotate right F (rotate right through carry) | 00 1101 d fffffff | RLF f,d | Rotate left F (rotate left through carry) | 00 1110 d fffffff | SWAPF f,d | Swap 4-bit halves of f (d = f<<4 | f>>4) | 00 1111 d fffffff | INCFSZ f,d | Increment f (d = f + 1) and skip if zero | | | 01 00 bbb fffffff | BCF f,b | Bit clear f (Clear bit b of f) | 01 01 bbb fffffff | BSF f,b | Bit set f (Set bit b of f) | 01 10 bbb fffffff | BTFSC f,b | Bit test f, skip if clear (Test bit b of f) | 01 11 bbb fffffff | BTFSS f,b | Bit test f, skip if set (Test bit b of f) | | | 10 0 kkkkkkkkkkk | CALL k | Save return address, load PC with k | 10 1 kkkkkkkkkkk | GOTO k | Jump to address k (11 bits) | | | 11 00xx kkkkkkkk | MOVLW k | Move literal to W (W = k) | 11 01xx kkkkkkkk | RETLW k | Set W to k and return | 11 1000 kkkkkkkk | IORLW k | Inclusive or literal with W (W = k OR W) | 11 1001 kkkkkkkk | ANDLW k | AND literal with W (W = k AND W) | 11 1010 kkkkkkkk | XORLW k | Exclusive or literal with W (W = k XOR W) | 11 110x kkkkkkkk | SUBLW k | Subtract W from literal (W = k - W) | 11 111x kkkkkkkk | ADDLW k | Add literal to W (W = k + W) |
PIC17 High End Core Devices
The 17 series never became popular and has been superseded by the PIC18 architecture. It is not recommended for new designs, and availability may be limited.
Improvements over earlier cores are 16-bit wide opcodes (allowing many new instructions), and a 16 level deep call stack. PIC17 devices were produced in packages from 40 to 68 pins.
The 17 series introduced a number of important new features:
- a memory mapped accumulator
- read access to code memory (table reads)
- direct register to register moves (prior cores needed to move registers through the accumulator)
- an external program memory interface to expand the code space
- an 8bit x 8bit hardware multiplier
- a second indirect register pair
- auto-increment/decrement addressing controlled by control bits in a status register (ALUSTA)
PIC18 High End Core Devices
Microchip introduced the PIC18 architecture in 2002. Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language.
The 18 series inherits most of the features and instructions of the 17 series, while adding a number of important new features:
- much deeper call stack (31 levels deep)
- the call stack may be read and written
- conditional branch instructions
- indexed addressing mode (PLUSW)
- extending the FSR registers to 12 bits, allowing them to linearly address the entire data address space
- the addition of another FSR register (bringing the number up to 3)
The auto increment/decrement feature was improved by removing the control bits and adding four new indirect registers per FSR. Depending on which indirect file register is being accessed it is possible to postdecrement, postincrement, or preincrement FSR; or form the effective address by adding W to FSR.
In more advanced PIC18 devices, an "extended mode" is available which makes the addressing even more favorable to compiled code:
- a new offset addressing mode; some addresses which were relative to the access bank are now interpreted relative to the FSR2 register
- the addition of several new instructions, notable for manipulating the FSR registers.
These changes were primarily aimed at improving the efficiency of a data stack implementation. If FSR2 is used either as the stack pointer or frame pointer, stack items may be easily indexed—allowing more efficient re-entrant code. Microchip C18 chooses to use FSR2 as a frame pointer.
PIC24 and dsPIC 16-bit Microcontrollers
In 2001 Microchip introduced the dsPIC series of chips, which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition.
Architecturally, although they share the PIC moniker, they are very different from the 8-bit PICs. The most notable differences are
- they feature a set of 16 working registers
- they fully support a stack in RAM, and do not have a hardware stack
- bank switching is not required to access RAM or special function registers
- data stored in program memory can be accessed directly using a feature called Program Space Visibility
- interrupt sources may be assigned to distinct handlers using an interrupt vector table
Some features are:
dsPICs can be programmed in C using a variant of gcc.
PIC32 32-bit Microcontrollers
In November 2007 Microchip introduced the new family of 32-bit microcontrollers.
The initial device line-up is based on the industry standard MIPS32 M4K Core. The device can be programmed using the , a variant of the GCC compiler. The first 18 models currently in production (PIC32MX3xx and PIC32MX4xx) are pin to pin compatible and share the same peripherals set with the PIC24FxxGA0xx family of (16-bit) devices allowing the use of common libraries, software and hardware tools.
The PIC32 architecture brings a number of new features to Microchip portfolio, including:
- The highest execution speed 80MIPS (90+ Dhristone MIPS @80MHz)
- The largest FLASH memory: 512kbyte
- One instruction per clock cycle execution
- The first cached processor
- Allows execution from RAM
- Full Speed Host/Dual Role and OTG USB capabilities
- Full JTAG and 2 wire programming and debugging
- Real time trace
Device Variants and Hardware Features
PIC devices generally feature:
- Sleep mode (power savings).
- Watchdog timer.
- Various crystal or RC oscillator configurations, or an external clock.
Variants
Within a series, there are still many device variants depending on what hardware resources the chip features.
- General purpose I/O pins.
- Internal clock oscillators.
- 8/16 Bit Timers.
- Internal EEPROM Memory.
- Synchronous/Asynchronous Serial Interface USART.
- MSSP Peripheral for I²C and SPI Communications.
- Capture/Compare and PWM modules.
- Analog-to-digital converters (up to ~1.0 MHz).
- USB, Ethernet, CAN interfacing support.
- External memory interface.
- Integrated analog RF front ends (PIC16F639, and rfPIC).
- KEELOQ Rolling code encryption peripheral (encode/decode)
- And many more.
Trends
The first generation of PICs with EPROM storage are almost completely replaced by chips with Flash memory. Likewise, the original 12-bit instruction set of the PIC1650 and its direct descendants has been superseded by 14-bit and 16-bit instruction sets. Microchip still sells OTP (one-time-programmable) and windowed (UV-erasable) versions of some of its EPROM based PICs for legacy support or volume orders. It should be noted that the Microchip website lists PICs that are not electrically erasable as OTP despite the fact that UV erasable windowed versions of these chips can be ordered.
History
The original PIC was built to be used with General Instruments' new 16-bit CPU, the CP1600. While generally a good CPU, the CP1600 had poor I/O performance, and the 8-bit PIC was developed in 1975 to improve performance of the overall system by offloading I/O tasks from the CPU. The PIC used simple microcode stored in ROM to perform its tasks, and although the term wasn't used at the time, it shares some common features with RISC designs.
In 1985 General Instruments spun off their microelectronics division, and the new ownership canceled almost everything — which by this time was mostly out-of-date. The PIC, however, was upgraded with internal EPROM to produce a programmable channel controller, and today a huge variety of PICs are available with various on-board peripherals (serial communication modules, UARTs, motor control kernels, etc.) and program memory from 256 words to 64k words and more (a "word" is one assembly language instruction, varying from 12, 14 or 16 bits depending on the specific PIC micro family).
PIC and PICmicro are registered trademarks of Microchip Technology. It is generally thought that PIC stands for Peripheral Interface Controller, although General Instruments' original acronym for the initial PIC1640 and PIC1650 devices was "Programmable Interface Controller". The acronym was quickly replaced with "Programmable Intelligent Computer".
The Microchip 16C84 (PIC16x84), introduced in 1993
was the first CPU with on-board EEPROM memory.
This electrically-erasable memory made it cost less than CPUs that required a quartz "erase window" for erasing EPROM.
Development Tools
Commercially Supported
Microchip provides a freeware IDE package called MPLAB, which includes an assembler, linker, software simulator, and debugger. They also sell C compilers for the PIC18 and dsPIC which integrate cleanly with MPLAB. Free student versions of the C compilers are also available with all features. But for the free versions, optimizations will be disabled after 60 days.
Several third parties make C, BASIC and Pascal language compilers for PICs, many of which integrate to MPLAB and/or feature their own IDE.
A blockset for Matlab/Simulink allow one to generate C and binary files from a simulink model. Most common peripherals have their blocksets and you do not need to write the configuration code.
Open Source
The following development tools are available for the PIC family under the GPL or other free software or open sources licenses.
FreeRTOS is a mini real time kernel ported to PIC18, PIC24, dsPIC and PIC32 architectures.
GPUTILS is free and available from the GPUTILS website.
GPSIM is an Open Source simulator for the PIC microcontrollers featuring hardware modules that simulate specific devices that might be connected to them, like LCDs.
SDCC supports 8-bit PIC micro controllers (PIC16, PIC18). Currently, throughout the SDCC website, the words, "Work is in progress", are frequently used to describe the status of SDCC's support for PICs.
is a free IDE for programming PIC Microcontroller. It allows one to write the program in C, Assembly, Microbe (a BASIC-like language) and using FlowChart Method.
PiKdev runs on Linux and is a simple graphic IDE for the development of PIC-based applications.
It currently supports assembly language. Non Open Source C language (Currently free 1/22/07) is also supported for PIC 18 devices.
PiKdev is developed in C++ under Linux and is based on the KDE environment.
Piklab is a forked version of PiKdev and is managed as SourceForge Project. Piklab adds to Pikdev by providing support for programmers and debuggers. Currently, Piklab supports the JDM, PIC Elmer, K8048, HOODMICRO, ICD1, ICD2, PICkit1, PICKkit2, and PicStart+ as programming devices and has debugging support for ICD2 in addition to using the simulator, GPSim.
JAL stands for Just Another Language. It is a Pascal-like language that is easily mastered. The compiler supports a few Microchip (16c84, 16f84, 12c508, 12c509, 16F877) and SX microcontrollers. The resulting assembly language can then be viewed, modified and further processed as if you were programming directly in assembler.
The GNU Compiler Collection and the GNU Binutils have been ported to the PIC24, dsPIC30F and dsPIC33F in the form of Microchip's compiler and Assembler.
MIOS is a real-time operating system written in PIC assembly, optimized for MIDI processing and other musical control applications. There is a C wrapper for higher level development. Currently it runs on the MIDIbox Hardware Platform.
FlashForth is a native Forth operating system for the PIC18F and the dsPIC30F series. It makes the PIC a standalone computer with an interpreter, compiler, assembler and multitasker.
Great Cow Basic (GCBasic) The syntax of Great Cow BASIC is based on that of QBASIC/FreeBASIC. The assembly code produced by Great Cow BASIC can be assembled and run on almost all 10, 12, 16 and 18 series PIC chips.
Device Programmers
Devices called "programmers" are traditionally used to get program code into the target PIC. Most PICs that Microchip currently sell feature ICSP (In Circuit Serial Programming) and/or LVP (Low Voltage Programming) capabilities, allowing the PIC to be programmed while it is sitting in the target circuit. ICSP programming is performed using two pins, clock and data, while a high voltage (12V) is present on the Vpp/MCLR pin. Low voltage programming dispenses with the high voltage, but reserves exclusive use of an I/O pin and can therefore be disabled to recover the pin for other uses (once disabled it can only be re-enabled using high voltage programming).
There are many programmers for PIC microcontrollers, ranging from the extremely simple designs which rely on ICSP to allow direct download of code from a host computer, to intelligent programmers that can verify the device at several supply voltages. Many of these complex programmers use a pre-programmed PIC themselves to send the programming commands to the PIC that is to be programmed. The intelligent type of programmer is needed to program earlier PIC models (mostly EPROM type) which do not support in-circuit programming.
Many of the higher end flash based PICs can also self-program (write to their own program memory). Demo boards are available with a small bootloader factory programmed that can be used to load user programs over an interface such as RS-232 or USB, thus obviating the need for a programmer device. Alternatively there is bootloader firmware available that the user can load onto the PIC using ICSP. The advantages of a bootloader over ICSP is the far superior programming speeds, immediate program execution following programming, and the ability to both debug and program using the same cable.
Microchip Programmers
There are many programmers/debuggers available directly from Microchip.
Current Microchip Programmers (as of 3/2009)
- PICStart Plus (RS232 serial interface) : intelligent.
- PRO MATE II (RS232 serial interface) : intelligent.
- MPLAB PM3 (RS232 serial and USB interface)
- MPLAB ICD2 (RS232 serial and USB 1.0 interface) : ICSP programming only
- MPLAB REAL ICE (USB 2.0 interface) : ICSP programming only
- PICKit 2 (USB interface)
- PICKit 3 (USB interface)
- ICD 3 (USB interface)
Legacy Microchip Programmers
Third-Party Programmers
There are programmers available from other sources, ranging from plans to build your own, to self-assembly kits and fully tested ready-to-go units. Some are simple designs which require a PC to do the low-level programming signalling (these typically connect to the serial or parallel port and consist of a few simple components), while others have the programming logic built into them (these typically use a serial or USB connection, are usually faster, and are often built using PICs themselves for control). For a directory of PIC related tools and websites, see . These are some common programmer types:
- Simple serial port ICSP programmers
- These generally rely on driving the PIC's Vss line negative to get the necessary voltage differences from programming. Hence they are compact and cheap but great care is needed if using them for in circuit programming.
- Simple parallel port ICSP programmers
- Simple to understand but often have much higher part counts and generally require external power supplies.
- Intelligent programmers (some use USB port)
- Generally faster and more reliable (especially on laptops which tend to have idiosyncrasies in the way they implement their ports) but far more complex to build (in particular they tend to use a PIC in the programmer which must itself be programmed somehow).
Here are some programmers available:
- usbpicprog, an open source USB PIC programmer
- Open Programmer, another open source USB programmer for PICmicro and I2C EEPROM, using HID class
- home-made ICSP
- PIC PRESTO that supports ICSP, ISP, JTAG, I2C, SPI, Microwire interfaces, works on USB and complies with programming specifications
- home-made ICSP with external powersupply based on JDM:
The major problem of home-made or very simple programmers is that these programmers do not comply with programming specifications and this can cause premature loss of data in the flash or EEPROM.
Debugging
Software Emulation
(which is a free download) includes a software emulator for PICs. However, software emulation of a microcontroller will always suffer from limited simulation of the device's interactions with its target circuit.
is a commercial software product developed by Labcenter Electronics which allows simulation of many PICmicro devices along with a wide array of peripheral devices. This method can help bridge the gap between the limited peripheral support offered by the MPLAB simulator and traditional in-circuit debugging/emulating. The product interfaces directly with MPLAB to offer a schematic display of signals and peripheral devices.
is a free and open source circuit simulator for KDE which features simulating some types of PIC microcontrollers besides many other analog and digital parts.
is a free and open source IDE for developing PIC software on KDE which is able to simulate and debug PIC software using another free and open source tool called as backend.
In-Circuit Debugging
Later model PICs feature an ICD (in-circuit debugging) interface, built into the CPU core. ICD debuggers (MPLAB ICD2 and other third party) can communicate with this interface using three lines. This cheap and simple debugging system comes at a price however, namely limited breakpoint count (1 on older pics 3 on newer PICs), loss of some IO (with the exception of some surface mount 44-pin PICs which have dedicated lines for debugging) and loss of some features of the chip. For small PICs, where the loss of IO caused by this method would be unacceptable, special headers are made which are fitted with PICs that have extra pins specifically for debugging.
In-Circuit Emulators
Microchip offers three full in circuit emulators: the MPLAB ICE2000 (parallel interface, a USB converter is available); the newer MPLAB ICE4000 (USB 2.0 connection); and most recently, the REAL ICE. All of these ICE tools can be used with the MPLAB IDE for full source-level debugging of code running on the target.
The ICE2000 requires emulator modules, and the test hardware must provide a socket which can take either an emulator module, or a production device.
The REAL ICE connects directly to production devices which support in-circuit emulation through the PGC/PGD programming interface, or through a high speed connection which uses two more pins. According to Microchip, it supports "most" flash-based PIC, PIC24, and dsPIC processors.
The ICE4000 is no longer directly advertised on Microchip's website, and the purchasing page states that it is not recommended for new designs.
PIC clones
8/16/32-bit PIC microcontroller product families
These links take you to product selection matrices at the manufacturer's site.
8-bit Microcontrollers
16-bit Microcontrollers
32-bit Microcontrollers
16-bit Digital Signal Controllers
The F in a name generally indicates the PICmicro uses flash memory and can be erased electronically. A C generally means it can only be erased by exposing the die to ultraviolet light (which is only possible if a windowed package style is used). An exception to this rule is the PIC16C84 which uses EEPROM and is therefore electrically erasable.
Security in Microchip PIC devices is known to be extremely weak. Reports have been published by about the weaknesses. These weaknesses repeat themselves across the entire line of devices.
See also
External links
- Official web site
- FAQ and Archive from the "PICList" email list hosted at MIT. A well respected source of manufacturer-independent solutions, source code, and expertise.
- Open Source assembler and linker.
- Free C, C++, Pascal, Basic compilers for the PIC microcontroller series.
- Example C code for the rfPIC
- example of robot controlled by PIC16F877A:
- An open source project for a universal PIC programmer
- A PIC microcontroller based Network I/O controller
- Enable GameBoy hardware to PIC16F877
- ZeroG develops Wi-Fi modules for PIC microcontrollers.
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