Message Signaled Interrupts, in
PCIConventional PCI is a computer bus for attaching hardware devices in a computer. These devices can take either the form of an integrated circuit fitted onto the motherboard itself, called a planar device in the PCI specification, or an expansion card that fits into a slot...
2.2
and later and
PCI ExpressPCI Express , officially abbreviated as PCIe , is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP standards...
, are an alternative way of generating an
interruptIn computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
. Traditionally, a device has an interrupt pin which it asserts when it wants to interrupt the host CPU. While PCI Express does not have separate interrupt pins, it has special messages to allow it to emulate a pin assertion or deassertion. Message Signaled Interrupts allow the device to write a small amount of data to a special address in memory space.
Message Signaled Interrupts, in
PCIConventional PCI is a computer bus for attaching hardware devices in a computer. These devices can take either the form of an integrated circuit fitted onto the motherboard itself, called a planar device in the PCI specification, or an expansion card that fits into a slot...
2.2
and later and
PCI ExpressPCI Express , officially abbreviated as PCIe , is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP standards...
, are an alternative way of generating an
interruptIn computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
. Traditionally, a device has an interrupt pin which it asserts when it wants to interrupt the host CPU. While PCI Express does not have separate interrupt pins, it has special messages to allow it to emulate a pin assertion or deassertion. Message Signaled Interrupts allow the device to write a small amount of data to a special address in memory space. The chipset will deliver the corresponding interrupt to a CPU.
A common misconception with Message Signaled Interrupts is that they allow the device to send data to the CPU as part of the interrupt. The data that is sent as part of the write is used by the chipset to determine which interrupt to trigger on which CPU; it is not available for the device to communicate additional information to the interrupt handler.
Some non-PCI architectures also use Message Signaled Interrupts. For example, HP
GSCGSC is a bus used in many of the HP 9000 workstations and servers. The acronym has various explanations, including Gecko System Connect , Gonzo System Connect and General System Connect....
devices do not have interrupt pins and can only interrupt by writing directly to the processor's interrupt register in memory space.
Advantages over pin-based interrupts
While more complex to implement in a device, MSI has some significant advantages.
On the mechanical side, fewer pins makes for a simpler, cheaper, and more reliable connector. While this is no advantage to the standard PCI connector, PCI Express takes advantage of this savings.
It raises the limits on the number of interrupts that are possible. While conventional PCI was limited to 4 interrupts per card (and,
because they were shared among all cards, most used just 1), message signaled interrupts allow dozens of interrupts per card, if that is useful.
There is also a slight performance advantage. In software, a pin-based interrupt could race with a posted write to memory. That is, the PCI device would write data to memory and then send an interrupt to indicate the
DMADirect memory access is a feature of modern computers and microprocessors that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. Many hardware systems use DMA including disk drive controllers,...
write was complete. However, a PCI bridge or memory controller might buffer the write in order to not interfere with some other memory use. The interrupt could arrive before the DMA write was complete, and the processor could read stale data from memory. To prevent this race, interrupt handlers were required to read from the device to ensure that the DMA write had finished. This read had a moderate performance penalty. An MSI write cannot pass a DMA write, so no read from the device is necessary to fix this race.
Original MSI
PCI defines two different extensions to support Message Signaled Interrupts, MSI and MSI-X.
MSI (defined in PCI 2.2) permits a device to allocate 1, 2, 4, 8, 16 or 32 interrupts. The device is programmed with an address to write to (generally a control register in an interrupt controller), and a 16-bit data word to identify it. The interrupt number is added to the data word to identify the interrupt.
MSI-X
The single address used by original MSI was found to be restrictive for some architectures. In particular, it made it difficult to target individual interrupts to different processors, which is helpful in some high-speed networking applications. MSI-X (defined in PCI 3.0) allows a larger number of interrupts (up to 2048), and gives each one a separate target address and data word.
Optional features in MSI (64-bit addressing and interrupt masking) are also mandatory with MSI-X.
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