Message Signaled Interrupts
Encyclopedia
Message Signaled Interrupts, in PCI
2.2
and later in PCI Express
, are an alternative way of generating an interrupt
. Traditionally, a device has an interrupt pin which it asserts when it wants to interrupt the host CPU. While PCI Express does not have separate interrupt pins, it has special messages to allow it to emulate a pin assertion or deassertion. Message Signaled Interrupts allow the device to write a small amount of data to a special address in memory space. The chipset will deliver the corresponding interrupt to a CPU.
A common misconception with Message Signaled Interrupts is that they allow the device to send data to the CPU as part of the interrupt. The data that is sent as part of the write is used by the chipset to determine which interrupt to trigger on which CPU; it is not available for the device to communicate additional information to the interrupt handler.
Some non-PCI architectures also use Message Signaled Interrupts. For example, HP GSC
devices do not have interrupt pins and can only interrupt by writing directly to the processor's interrupt register in memory space.
On the mechanical side, fewer pins makes for a simpler, cheaper, and more reliable connector. While this is no advantage to the standard PCI connector, PCI Express takes advantage of these savings.
MSI increases the number of interrupts that are possible. While conventional PCI was limited to 4 interrupts per card (and,
because they were shared among all cards, most used just 1), message signaled interrupts allow dozens of interrupts per card, when that is useful.
There is also a slight performance advantage. In software, a pin-based interrupt could race
with a posted write to memory. That is, the PCI device would write data to memory and then send an interrupt to indicate the DMA
write was complete. However, a PCI bridge or memory controller might buffer the write in order to not interfere with some other memory use. The interrupt could arrive before the DMA write was complete, and the processor could read stale data from memory. To prevent this race, interrupt handlers were required to read from the device to ensure that the DMA write had finished. This read had a moderate performance penalty. An MSI write cannot pass a DMA write, so the race is eliminated.
Optional features in MSI (64-bit addressing and interrupt masking) are also mandatory with MSI-X.
Peripheral Component Interconnect
Conventional PCI is a computer bus for attaching hardware devices in a computer...
2.2
and later in PCI Express
PCI Express
PCI Express , officially abbreviated as PCIe, is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP bus standards...
, are an alternative way of generating an interrupt
Interrupt
In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
. Traditionally, a device has an interrupt pin which it asserts when it wants to interrupt the host CPU. While PCI Express does not have separate interrupt pins, it has special messages to allow it to emulate a pin assertion or deassertion. Message Signaled Interrupts allow the device to write a small amount of data to a special address in memory space. The chipset will deliver the corresponding interrupt to a CPU.
A common misconception with Message Signaled Interrupts is that they allow the device to send data to the CPU as part of the interrupt. The data that is sent as part of the write is used by the chipset to determine which interrupt to trigger on which CPU; it is not available for the device to communicate additional information to the interrupt handler.
Some non-PCI architectures also use Message Signaled Interrupts. For example, HP GSC
GSC bus
GSC is a bus used in many of the HP 9000 workstations and servers. The acronym has various explanations, including Gecko System Connect , Gonzo System Connect and General System Connect....
devices do not have interrupt pins and can only interrupt by writing directly to the processor's interrupt register in memory space.
Advantages over pin-based interrupts
While more complex to implement in a device, MSI has some significant advantages.On the mechanical side, fewer pins makes for a simpler, cheaper, and more reliable connector. While this is no advantage to the standard PCI connector, PCI Express takes advantage of these savings.
MSI increases the number of interrupts that are possible. While conventional PCI was limited to 4 interrupts per card (and,
because they were shared among all cards, most used just 1), message signaled interrupts allow dozens of interrupts per card, when that is useful.
There is also a slight performance advantage. In software, a pin-based interrupt could race
Race condition
A race condition or race hazard is a flaw in an electronic system or process whereby the output or result of the process is unexpectedly and critically dependent on the sequence or timing of other events...
with a posted write to memory. That is, the PCI device would write data to memory and then send an interrupt to indicate the DMA
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....
write was complete. However, a PCI bridge or memory controller might buffer the write in order to not interfere with some other memory use. The interrupt could arrive before the DMA write was complete, and the processor could read stale data from memory. To prevent this race, interrupt handlers were required to read from the device to ensure that the DMA write had finished. This read had a moderate performance penalty. An MSI write cannot pass a DMA write, so the race is eliminated.
MSI types
PCI defines two optional extensions to support Message Signaled Interrupts, MSI and MSI-X. While PCIe is software compatible with legacy interrupts it requires MSI or MSI-X.MSI
MSI (first defined in PCI 2.2) permits a device to allocate 1, 2, 4, 8, 16 or 32 interrupts. The device is programmed with an address to write to (generally a control register in an interrupt controller), and a 16-bit data word to identify it. The interrupt number is added to the data word to identify the interrupt. Some platforms such as Windows do not use all 32 interrupts but only use up to 16 interrupts.MSI-X
MSI-X (first defined in PCI 3.0) permits a device to allocate up to 2048 interrupts. The single address used by original MSI was found to be restrictive for some architectures. In particular, it made it difficult to target individual interrupts to different processors, which is helpful in some high-speed networking applications. MSI-X allows a larger number of interrupts and gives each one a separate target address and data word. Devices with MSI-X do not necessarily support 2048 interrupts but at least 64 which is double than the maximum MSI interrupts.Optional features in MSI (64-bit addressing and interrupt masking) are also mandatory with MSI-X.
External links
- MSDN paper on MSI in Windows Vista
- Linux MSI HOWTO
- Changes required to support MSI in FreeBSD (MSI / MSI-X Supported as of FreeBSD 6.3-RELEASE)
- Changes made to support MSI in Solaris Express
- Charlie Chen's Weblog: how does MSI-X work