Functional verification, in electronic design automation

Electronic design automation

Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...

, is the task of verifying that the logic design

Digital circuit

Digital electronics represent signals by discrete bands of analog levels, rather than by a continuous range. All levels within a band represent the same signal state...

 conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and takes the majority of time and effort in most large electronic system design projects.

Functional verification is very difficult because of the sheer volume of possible testcases that exist in even a simple design. Frequently there are more than 10^80 possible tests to comprehensively verify a design - a number that is impossible to achieve in a lifetime. This effort is equivalent to program verification, and is NP-hard

NP-hard

NP-hard , in computational complexity theory, is a class of problems that are, informally, "at least as hard as the hardest problems in NP". A problem H is NP-hard if and only if there is an NP-complete problem L that is polynomial time Turing-reducible to H...

 or even worse - and no solution has been found that works well in all cases. However, it can be attacked by many methods. None of them are perfect, but each can be helpful in certain circumstances:

• Logic simulation
  Logic simulation
  Logic simulation is the use of a computer program to simulate the operation of a digital circuit. Logic simulation is the primary tool used for verifying the logical correctness of a hardware design. In many cases logic simulation is the first activity performed in the process of taking a hardware...
  
   simulates the logic before it is built.
• Simulation acceleration applies special purpose hardware to the logic simulation problem.
• Emulation builds a version of system using programmable logic. This is expensive, and still much slower than the real hardware, but orders of magnitude faster than simulation. It can be used, for example, to boot the operating system on a processor.
• Formal verification
  Formal verification
  In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics .- Usage :Formal verification can be...
  
   attempts to prove mathematically that certain requirements (also expressed formally) are met, or that certain undesired behaviors (such as deadlock) cannot occur.
• Intelligent verification
  Intelligent verification
  Intelligent Verification, also referred to as intelligent testbench automation, is a form of functional verification used to verify that an electronic hardware design conforms to specification before device fabrication...
  
   uses automation to adapt the testbench to changes in the register transfer level
  Register transfer level
  In integrated circuit design, register-transfer level is a level of abstraction used in describing the operation of a synchronous digital circuit...
  
   code.
• HDL-specific versions of lint
  Lint programming tool
  In computer programming, lint was the name originally given to a particular program that flagged some suspicious and non-portable constructs in C language source code. The term is now applied generically to tools that flag suspicious usage in software written in any computer language...
  
  , and other heuristics, are used to find common problems.

Simulation based verification (also called 'dynamic verification') is widely used to "simulate" the design, since this method scales up very easily. Stimulus is provided to exercise each line in the HDL code. A test-bench is built to functionally verify the design by providing meaningful scenarios to check that given certain input, the design performs to specification.

A simulation environment is typically composed of several types of components:

• The generator
  Random test generator
  Random test generators are a type of computer software that is used in functional verification of microprocessors. Their primary use lies in providing input stimulus to a device under test....
  
   (or irritator) generates input vectors that are used to search for anomalies that exist between the intent (specifications) and the implementation (HDL Code). This type of generator utilizes an NP-complete type of SAT Solver that can be computationally expensive. Other types of generators include manually created vectors, Graph-Based generators (GBMs) proprietary generators. Modern generators create directed-random and random stimuli that are statistically driven to verify random parts of the design. The randomness is important to achieve a high distribution over the huge space of the available input stimuli. To this end, users of these generators intentionally under-specify the requirements for the generated tests. It is the role of the generator to randomly fill this gap. This mechanism allows the generator to create inputs that reveal bugs not being searched for directly by the user. Generators also bias the stimuli toward design corner cases to further stress the logic. Biasing and randomness serve different goals and there are tradeoffs between them, hence different generators have a different mix of these characteristics. Since the input for the design must be valid (legal) and many targets (such as biasing) should be maintained, many generators use the Constraint satisfaction problem
  Constraint satisfaction problem
  Constraint satisfaction problems s are mathematical problems defined as a set of objects whose state must satisfy a number of constraints or limitations. CSPs represent the entities in a problem as a homogeneous collection of finite constraints over variables, which is solved by constraint...
  
   (CSP) technique to solve the complex testing requirements. The legality of the design inputs and the biasing arsenal are modeled. The model-based generators use this model to produce the correct stimuli for the target design.
• The drivers
  Device driver
  In computing, a device driver or software driver is a computer program allowing higher-level computer programs to interact with a hardware device....
  
   translate the stimuli produced by the generator into the actual inputs for the design under verification. Generators create inputs at a high level of abstraction, namely, as transactions or assembly language. The drivers convert this input into actual design inputs as defined in the specification of the design's interface.
• The simulator produces the outputs of the design, based on the design’s current state (the state of the flip-flops) and the injected inputs. The simulator has a description of the design net-list. This description is created by synthesizing the HDL to a low gate level net-list.
• The monitor
  Machine code monitor
  A machine code monitor is software built into or separately available for various computers, allowing the user to enter commands to view and change memory locations on the machine, with options to load and save memory contents from/to secondary storage.Machine code monitors became something of a...
  
   converts the state of the design and its outputs to a transaction abstraction level so it can be stored in a 'score-boards' database to be checked later on.
• The checker validates that the contents of the 'score-boards' are legal. There are cases where the generator creates expected results, in addition to the inputs. In these cases, the checker must validate that the actual results match the expected ones.
• The arbitration manager manages all the above components together.

Different coverage

Code coverage

Code coverage is a measure used in software testing. It describes the degree to which the source code of a program has been tested. It is a form of testing that inspects the code directly and is therefore a form of white box testing....

 metrics are defined to assess that the design has been adequately exercised. These include functional coverage (has every functionality of the design been exercised?), statement coverage (has each line of HDL been exercised?), and branch coverage (has each direction of every branch been exercised?).

Functional Verification Tools

• Avery Design Systems: SimCluster (for parallel logic simulation) and Insight (for formal verification)
• Breker Verification Systems, Inc.: Trek (a model-based test generation tool for complex SoCs)
• Cadence Design Systems
  Cadence Design Systems
  Cadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...
  
  
• EVE/ZeBu
  EVE/ZeBu
  EVE/ZeBu is a leading provider of hardware-assisted verification tools for functional verification of Application-specific integrated circuits and system on chip designs and for validation of embedded software ahead of implementation in silicon...
  
  
• Mentor Graphics
  Mentor Graphics
  Mentor Graphics, Inc is a US-based multinational corporation dealing in electronic design automation for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create...
  
  
• Nusym Technology
  Nusym Technology
  Nusym Technology, Inc. is a company that produces intelligent verification software products, also known as intelligent testbench products, which are a form of functional verification that targets and maximizes test coverage of a logic design by automatically adapting the verification testbenches...
  
  
• Obsidian Software
• Synopsys
  Synopsys
  Synopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
  
  

External links

You can find related articles in

• http://www.thinkverification.com/
• CFS Vision Project: http://www.cfs-vision.com/
• An IDE for e and SystemVerilog: http://www.dvteclipse.com/