Double data rateIn computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....
synchronous dynamic random access memorySynchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
(DDR SDRAM) is a class of memory
integrated circuitAn integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
s used in
computerA computer is a programmable machine designed to sequentially and automatically carry out a sequence of arithmetic or logical operations. The particular sequence of operations can be changed readily, allowing the computer to solve more than one kind of problem...
s. DDR SDRAM (sometimes referred to as
DDR1 SDRAM) has been superseded by
DDR2 SDRAMDDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
and
DDR3 SDRAMIn computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
, neither of which are either
forwardForward compatibility or upward compatibility is a compatibility concept for systems design, as e.g. backward compatibility. Forward compatibility aims at the ability of a design to gracefully accept input intended for later versions of itself...
or
backward compatibleIn the context of telecommunications and computing, a device or technology is said to be backward or downward compatible if it can work with input generated by an older device...
with DDR SDRAM, meaning that DDR2 or DDR3
memory moduleMemory module is a broad term used to refer to a series of dynamic random access memory integrated circuits modules mounted on a printed circuit board and designed for use in personal computers, workstations and servers....
s will not work in DDR equipped
motherboardIn personal computers, a motherboard is the central printed circuit board in many modern computers and holds many of the crucial components of the system, providing connectors for other peripherals. The motherboard is sometimes alternatively known as the mainboard, system board, or, on Apple...
s, and vice versa.
Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as
phase-locked loopA phase-locked loop or phase lock loop is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector...
s and self-calibration to reach the required timing accuracy. The interface uses
double pumpingIn computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....
(transferring data on both the rising and falling edges of the
clock signalIn electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
) to lower the clock frequency. One advantage of keeping the clock frequency down is that it reduces the
signal integritySignal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise,...
requirements on the circuit board connecting the memory to the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the
bandwidthIn computer networking and computer science, bandwidth, network bandwidth, data bandwidth, or digital bandwidth is a measure of available or consumed data communication resources expressed in bits/second or multiples of it .Note that in textbooks on wireless communications, modem data transmission,...
of a single data rate (SDR)
SDRAMSynchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
running at the same clock frequency, due to this double pumping.
With data being transferred 64
bitA bit is the basic unit of information in computing and telecommunications; it is the amount of information stored by a digital device or other physical system that exists in one of two possible distinct states...
s at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.
"Beginning in 1996 and concluding in June 2000,
JEDECThe JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
developed the DDR (Double Data Rate) SDRAM specification (JESD79)." JEDEC has set standards for data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules.
Specification standards
Chips and modules
Standard name
|
Memory clock
(MHz) |
Cycle time
(ns) |
I/O bus clock
(MHz) |
Data rate
(MT/s) |
VDDQ
(V) |
Module name
|
Peak transfer rate
(MB/s) |
Timings
(CL-tRCD-tRP) |
| DDR-200 |
100 |
10 |
100 |
200 |
2.5±0.2 |
PC-1600 |
1600 |
| DDR-266 |
133⅓ |
7.5 |
133⅓ |
266⅔ |
PC-2100 |
2133⅓ |
| DDR-333 |
166⅔ |
6 |
166⅔ |
333⅓ |
PC-2700 |
2666⅔ |
DDR-400A
DDR-400B
DDR-400C |
200 |
5 |
200 |
400 |
2.6±0.1 |
PC-3200 |
3200 |
2.5-3-3
3-3-3
3-4-4 |
Note: All above listed are specified by
JEDECThe JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
as JESD79F. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using tighter-tolerance or overvolted chips.
The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.
There is no architectural difference between DDR SDRAM designed for different clock frequencies, for example, PC-1600, designed to run at 100 MHz, and PC-2100, designed to run at 133 MHz. The number simply designates the data rate at which the chip is guaranteed to perform, hence DDR SDRAM is guaranteed to run at lower (
underclockingUnderclocking, also known as downclocking, is the practice of modifying a synchronous circuit's timing settings to run at a lower clock rate than it was specified to operate at. It may be said to be the computer equivalent of driving a car below the speed limit...
) and can possibly run at higher (
overclockingOverclocking is the process of operating a computer component at a higher clock rate than it was designed for or was specified by the manufacturer, but some manufacturers purposely underclock their components to improve battery life. Many people just overclock or 'rightclock' their hardware to...
) clock rates than those for which it was made.
DDR SDRAM modules for desktop computers, commonly called
DIMMA DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
s, have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers,
SO-DIMMA SO-DIMM, or small outline dual in-line memory module, is a type of computer memory built using integrated circuits.SO-DIMMs are a smaller alternative to a DIMM, being roughly half the size of regular DIMMs...
s, have 200 pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion if unsure of a correct match. DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power consumption. Chips and modules with DDR-400/PC-3200 standard have a nominal voltage of 2.6 V.
Increasing operating voltage slightly can increase maximum speed, at the cost of higher power dissipation and heating, and at the risk of malfunctioning or damage.
Many new chipsets use these memory types in multi-channel configurations.
Chip characteristics
DRAM density: Size of the chip are measured in megabits (1 megabyte = 8 megabits. For example, 256 Mbit means 32
MBThe megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: bytes generally for computer memory; and one million bytes generally for computer storage. The IEEE Standards Board has decided that "Mega will mean 1 000...
.) Nearly all motherboards only recognize 1 GB modules if they contain
64M×8 chips
(low density ). If
128M×4 (high density) 1 GB modules are used, they most likely will not work. The
JEDECThe JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
standard allows
128M×4 only for slower buffered/registered modules designed specifically for some servers, but some generic manufacturers do not comply.
Organization: The notation like
64M×4 means that the memory matrix has 64 million (the product of
banks x
rows x
columns) 4-bit storage locations. There are
×4, ×8, and
×16 DDR chips. The
×4 chips allow the use of advanced error correction features like
ChipkillChipkill is IBM's trademark for a form of advanced error checking and correcting computer memory technology that protects computer memory systems from any single memory chip failure as well as multi-bit errors from any portion of a single memory chip...
,
memory scrubbingMemory scrubbing is the process of detecting and correcting bit errors in computer memory by using error-detecting codes like ECC.-Motivation for scrubbing:...
and Intel SDDC in server environments, while the
×8 and
×16 chips are somewhat less expensive.
x8 chips are mainly used in desktops/notebooks but are making entry into the server market. There are normally 4 banks and only one row can be active in each bank.
Module characteristics
Ranks:
To increase memory capacity and bandwidth, chips are combined on a module. For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed in parallel. Multiple chips with the common address lines are called a
memory rankA memory rank is a set of DRAMs connected to the same chip select, and which are therefore accessed simultaneously. In practice they also share all of the other command and control signals, and only the data pins for each DRAM are separate .The term “rank” was created and defined by JEDEC, the...
. The term was introduced to avoid confusion with chip internal
rows and
banks. A memory module may bear more than one rank. The term
sides would also be confusing because it incorrectly suggests the physical placement of chips on the module.
All ranks are connected to the same memory bus (address+data). The
Chip SelectChip select or slave select is the name of a control line in digital electronics used to select one chip out of several connected to the same computer bus usually utilizing the three-state logic....
signal is used to issue commands to specific rank.
Adding modules to the single memory bus creates additional electrical load on its drivers. To mitigate the resulting bus signaling rate drop and overcome the memory bottleneck, new chipsets employ the multi-channel architecture.
Capacity
Number of DRAM Devices: The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy one side (
single sided) or both sides (
dual sided) of the module. The maximum number of chips per DDR module is 36 (9×4) for ECC and 32 (8x4) for non-ECC.
ECC vs non-ECC: Modules that have error correcting code are labeled as ECC. Modules without error correcting code are labeled
non-ECC.
Timings:
CAS latencyColumn Address Strobe latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins...
(CL), clock cycle time (t
CK), row cycle time (t
RC), refresh row cycle time (t
RFC), row active time (
tRAS).
Buffering:
registeredRegistered memory modules have a register between the DRAM modules and the system's memory controller. They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise...
(or buffered) vs
unbufferedUnbuffered memory is RAM where there is no hardware register between the memory controller and the RAM chips. Unbuffered memory is the opposite of registered memory. Registered memory is more stable, one clock cycle slower, and more expensive than unbuffered memory...
Packaging: Typically
DIMMA DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
or
SO-DIMMA SO-DIMM, or small outline dual in-line memory module, is a type of computer memory built using integrated circuits.SO-DIMMs are a smaller alternative to a DIMM, being roughly half the size of regular DIMMs...
Power consumption: A test with DDR and DDR2 RAM in 2005 found that average power consumption appeared to be of the
orderAn order of magnitude is the class of scale or magnitude of any amount, where each class contains values of a fixed ratio to the class preceding it. In its most common usage, the amount being scaled is 10 and the scale is the exponent being applied to this amount...
of 1-3W per 512MB stick. Increases with clock rate, and when in use rather than idling. A manufacturer has produced calculators to estimate the power used by various types of RAM.
Module and chip characteristics are inherently linked.
Total module capacity is a product of one chip's capacity by the number of chips. ECC modules multiply it by 8/9 because they use one bit per byte for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.
DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip by number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently a module with greater amount of chips or using ×8 chips instead of ×4 will have more ranks.
Example: Variations of 1 GB PC2100 Registered DDR SDRAM module with ECC
| Module size (GB) |
Number of chips |
Chip size (Mbit) |
Chip organization |
Number of ranks |
| 1 |
36 |
256 |
64M×4 |
2 |
| 1 |
18 |
512 |
64M×8 |
2 |
| 1 |
18 |
512 |
128M×4 |
1 |
This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory modules, because all these variations can be sold under one price position without stating whether they are ×4 or ×8, single or dual ranked.
There is a common belief that number of module ranks equals number of sides. As above data shows, this is not true. One can find 2-side/1-rank or 2-side/4-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but it's unlikely such a module was ever produced.
Double data rate (DDR) SDRAM specification
From JEDEC Board Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametrics.
Standard No. 79 Revision Log:
- Release 1, June 2000
- Release 2, May 2002
- Release C, March 2003 – JEDEC Standard No. 79C.
"This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well."
High density vs low density
High density memory here means non-ECC 184 pin SDRAM memory.
Organization
PC3200 is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. Because PC3200 memory transfers data on both the rising and falling clock edges, its effective clock rate is 400 MHz.
1 GB PC3200 non-ECC modules are usually made with sixteen 512 Mbit chips, 8 down each side (512 Mbits × 16 chips) / (8 bits (per byte)) = 1,024 MB. The individual chips making up a 1 GB memory module are usually organized with 64 Mbits and a data width of 8 bits for each chip, commonly expressed as 64M×8. Memory manufactured in this way is low density RAM and will usually be compatible with any motherboard specifying PC3200 DDR-400 memory.
High density RAM
In the context of the 1 GB non-ECC PC3200 SDRAM module, there is very little visually to differentiate low density from high density RAM. High density DDR RAM modules will, like their low density counterparts, usually be
double-sidedDouble-sided RAM is a type of random-access memory which has its chips divided into two sides , only one of which can be seen at a time by the computer. Initially, these were created by essentially attaching two single-sided SIMM cards to the same PCB, but more modern chips use different wiring...
with eight 512 Mbit chips per side. The difference is that for each chip, instead of being organized in a 64M×8 configuration, it is organized with 128 Mbits and a data width of 4 bits, or 128M×4.
High density memory modules are assembled using chips from multiple manufacturers. These chips come in both the familiar 22 × 10 mm (approx.) TSOP2 and smaller squarer 12 × 9 mm (approx.) FBGA package sizes. High density chips can be identified by the numbers on each chip.
High density RAM devices were designed to be used in registered memory modules for servers. JEDEC standards do not apply to high-density DDR RAM in desktop implementations. JEDEC's technical documentation, however, supports 128M×4 semiconductors as such that contradicts 128×4 being classified as high density. As such,
high density is a relative term, which can be used to describe memory which is not supported by a particular motherboard's memory controller.
Alternatives
DDR SDRAM
Standard |
Bus clock
(MHz) |
Internal rate
(MHz) |
Prefetch
(min burst) |
Transfer Rate
(MT/s) |
Voltage |
DIMM A DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
pins |
SO-DIMM A SO-DIMM, or small outline dual in-line memory module, is a type of computer memory built using integrated circuits.SO-DIMMs are a smaller alternative to a DIMM, being roughly half the size of regular DIMMs...
pins |
MicroDIMM
pins |
| DDR |
100–200 |
100–200 |
2n |
200–400 |
2.5/2.6 |
184 |
200 |
172 |
| DDR2 DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
|
200–533 |
100–266 |
4n |
400–1066 |
1.8 |
240 |
200 |
214 |
DDR3In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
|
400–1066 |
100–266 |
8n |
800–2133 |
1.5 |
240 |
204 |
214 |
DDR : (DDR1) has been superseded by
DDR2 SDRAMDDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR2 are
RambusRambus Incorporated , founded in 1990, is a technology licensing company. The company became well known for its intellectual property based litigation following the introduction of DDR-SDRAM memory.- History :...
XDR DRAMXDR DRAM or extreme data rate dynamic random access memory is a high-performance RAM interface and successor to the Rambus RDRAM it is based on, competing with the rival DDR2 SDRAM and GDDR4 technology. XDR was designed to be effective in small, high-bandwidth consumer systems, high-performance...
. DDR2 has become the standard, as XDR is lacking support.
DDR3 SDRAMIn computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
is a new standard that offers even higher performance and new features.
DDR's prefetch buffer depth is 2 bits, while DDR2 uses 4 bits. Although the effective clock rates of DDR2 are higher than for DDR, the overall performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became
available.
Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz (i.e. 400MT/s and 200MHz external Clock). DDR2 picks up where DDR1 leaves off, and is available at effective clock rates of 400 MHz and higher.
RDRAMDirect Rambus DRAM or DRDRAM is a type of synchronous dynamic RAM. RDRAM was developed by Rambus inc., in the mid-1990s as a replacement for then-prevalent DIMM SDRAM memory architecture....
is a particularly expensive alternative to DDR SDRAM, and most manufacturers have dropped its support from their chipsets. DDR1 memory's prices have substantially increased since Q2 2008 while DDR2 prices are reaching an all-time low. In January 2009, 1 GB DDR1 is 2–3 times more expensive than 1 GB DDR2. High density DDR RAM will suit about 10% of PC motherboards on the market while low density will suit almost all motherboards on the PC Desktop market.
MDDR
MDDR is an acronym that some enterprises use for
Mobile DDRMobile DDR is type of double data rate synchronous DRAM for mobile computers.-Original LPDDR:...
SDRAM, a type of memory used in some portable electronic devices, like
mobile phoneA mobile phone is a device which can make and receive telephone calls over a radio link whilst moving around a wide geographic area. It does so by connecting to a cellular network provided by a mobile network operator...
s, handhelds, and digital audio players. Through techniques including reduced voltage supply and advanced refresh options,
Mobile DDRMobile DDR is type of double data rate synchronous DRAM for mobile computers.-Original LPDDR:...
can achieve greater power efficiency.
External links