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Alpha 21364
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The Alpha 21364, code-named "Marvel", also known as EV7, is a microprocessor developed by Compaq that implemented the Alpha instruction set architecture (ISA).
History
The Alpha 21364 was revealed in October 1998 by Compaq at the 11th Annual Microprocessor Forum. It was expected to be taped-out in late 1999, with samples available in early 2000 and volume shipments in late 2000.
At the 11th Annual Microprocessor Forum, it was described was an Alpha 21264 with a 1.5 MB 6-way set-associative on-die secondary cache, an integrated Direct Rambus DRAM memory controller and an integrated network controller for connecting to other microprocessors.
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Encyclopedia
The Alpha 21364, code-named "Marvel", also known as EV7, is a microprocessor developed by Compaq that implemented the Alpha instruction set architecture (ISA).
History
The Alpha 21364 was revealed in October 1998 by Compaq at the 11th Annual Microprocessor Forum. It was expected to be taped-out in late 1999, with samples available in early 2000 and volume shipments in late 2000.
At the 11th Annual Microprocessor Forum, it was described was an Alpha 21264 with a 1.5 MB 6-way set-associative on-die secondary cache, an integrated Direct Rambus DRAM memory controller and an integrated network controller for connecting to other microprocessors. Changes the Alpha 21264 core included a larger victim buffer, which was quadrupled in capacity to 32 entries, 16 for the Dcache and 16 for the Scache. It was reported by the Microprocessor Report that Compaq considered implementing minor changes to branch predictor to improve branch prediction accuracy and doubling the miss buffer in capacity to 16 entries instead of 8 in the Alpha 21264.
The original schedule was delayed, with the tape-out in April 2001 instead of late 1999. The Alpha 21364 was introduced in January 2002, operating at 1.25 GHz. Unlike previous Alpha microprocessors, the Alpha 21364 was not sold on the market. Systems using the Alpha 21364 from HP used models operating at 1.0 GHz. A 1.15 GHz Alpha 21364 was introduced on 16 August 2004 as part of the introduction of the EV7z.
The Alpha 21364 was originally intended to be succeeded by the Alpha 21464, code-named EV8, an entirely new implementation of the Alpha ISA with four-way simultaneous multithreading (SMT). It was first presented in 1999 at the 12th Annual Microprocessor Forum, but was cancelled in June 2001 at a late stage of development.
Development
The development of the Alpha 21364 was most focused on features that would improve memory performance, as the result of column written by Richard L. Sites, the chief architect of the Alpha Architecture. The column concluded that, "Over the coming decade, memory subsystem design will be the only important design issue for microprocessors."
Description
The Alpha 21364 was an Alpha 21264 with a 1.75 MB on-die secondary cache, two integrated memory controllers and an integrated network controller.
Core
The Alpha 21364's core is based on the EV68CB, a derivative of the Alpha 21264. The only modification was a larger victim buffer, now quadrupled in capacity to 32 entries. The 32 entries of victim buffer is divided equally into 16 entries each for the Dcache and Scache. Although the Alpha 21364 is a fourth-generation implementation of the Alpha Architecture, aside from this modification, the core is otherwise identical to that in the EV68CB derivative of the Alpha 21264.
Scache
The secondary cache (termed "Scache") has a capacity of 1.75 MB and is 7-way set associative. The cache protected by single-bit error correction, double-bit error detection (SECDED) error-correcting code (ECC). A 128-bit data path connects the cache to the cache controller. Access to the cache is fully pipelined so the data path yields a sustainable bandwidth of 16 GB/s at 1.0 GHz. The time required for data requested from the cache to when it can be used is 12 clock cycles.
Memory controller
The Alpha 21364 has two integrated memory controllers, each providing five RDRAM channels that support PC800 Rambus inline memory modules (RIMMs). The memory controller's fifth channel is used to provide RAID-like redudancy. Each channel is 16 bits wide and operates at 400 MHz. The total memory bandwidth of the eight RDRAM channels is 6.4 GB/s.
R-box
The R-box contains the network router. The network router connected the microprocessor to other microprocessors using four ports named North, South, East and West. Each port consisted of two 16-bit unidirectional links operating at 400 MHz. The network router also provided a fifth port for I/O, which consisted of two unidirectional 32-bit links operating at 200 MHz, yielding a peak bandwidth of 3.2 GB/s. The I/O port links are twice as wide and operate at half the clock frequency to simplify the design of the I/O ASIC.
The Alpha 21364 can connect to other microprocessors using various network topologies, such as a 3D torus. In multiprocessing systems, each microprocessor is a node with its own memory. Accessing the memory of other nodes is possible, but with a latency. The latency increases with distance, thus the Alpha 21364 implements non-uniform memory access multiprocessing. I/O was also non-uniform.
Fabrication
The Alpha 21364 contained 152 million transistors on a die with an area of 397 mm2. It was fabricated by International Business Machines (IBM) in a 0.18 µm complementary metal–oxide–semiconductor (CMOS) process with seven levels of interconnect. It was packaged in a 1443-contact flip-chip land grid array (LGA). It used a 1.65 V power supply and a 1.5 V external interface for a maximum power dissipation of 135 W at 1.25 GHz.
Alpha 21364A
The Alpha 21364A, code-named EV79, previously EV78, was a further development of the Alpha 21364. Intended to be the last Alpha microprocessor, with an introduction date in 2004, it was cancelled on 23 October 2003, with HP citing performance and schedule issues as reasons. A prototype was presented at the International Solid State Circuits Conference in 2003, operating at 1.45 GHz. Improvements included higher clock frequencies in the range of ~1.6 to ~1.7 GHz and support for 1066 Mbit/s RDRAM memory. It was to be fabricated in a 0.13 µm silicon on insulator (SOI) process. Power supply voltage was to be reduced to 1.2 V.
EV7z
The EV7z was a further development of the Alpha 21364. The EV7z became known on 23 October 2003 when HP announced that it had cancelled the Alpha 21364A and would be replacing it with the EV7z. Compared to the Alpha 21364, the EV7z was 14 to 16 percent faster, but was still slower than the Alpha 21364A it replaced, which was estimated to outperform the Alpha 21364 by 25 percent at 1.5 GHz. The EV7z was introduced on 16 August 2004. It was discontinued on 27 April 2007, alongside the AlphaServer GS1280. The EV7z was the last Alpha microprocessor to be developed and introduced. It operated at 1.3 GHz, supported PC1066 RIMMs and was fabricated in the same 0.18 µm process as the Alpha 21364. The only user of the EV7z was HP, who used it in their AlphaServer GS1280 server.
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