|
|
|
|
AMD Fusion
|
| |
|
| |
AMD Fusion is the codename for a future next-generation microprocessor design and the product of the merger between AMD and ATI, combining general processor execution as well as 3D geometry processing and other functions of modern GPUs into a single package. AMD's merger with ATI closed on October 25 2006. This technology is expected to debut in the second half of 2011 ; as a successor of the latest microarchitecture.
Regarding future AMD microarchitectures beyond the introduction of the latest microarchitecture at mid-2007 and a refresh of the microarchitecture in late 2007 and early 2008; AMD executive VP Henri Richard's June 2006 interview with DigiTimes hints at the future processor development beyond that of the well documented one:
n interview with Exec VP of AMD, Mario Rivas, CRN.com claims that: "'With its Fusion program, AMD hopes to deliver multicore products using different kinds of processing blocks.
Discussion
Ask a question about 'AMD Fusion' Start a new discussion about 'AMD Fusion' Answer questions from other users |
Encyclopedia
AMD Fusion is the codename for a future next-generation microprocessor design and the product of the merger between AMD and ATI, combining general processor execution as well as 3D geometry processing and other functions of modern GPUs into a single package. AMD's merger with ATI closed on October 25 2006. This technology is expected to debut in the second half of 2011 ; as a successor of the latest microarchitecture.
Regarding future AMD microarchitectures beyond the introduction of the latest microarchitecture at mid-2007 and a refresh of the microarchitecture in late 2007 and early 2008; AMD executive VP Henri Richard's June 2006 interview with DigiTimes hints at the future processor development beyond that of the well documented one:
Motivation
In an interview with Exec VP of AMD, Mario Rivas, CRN.com claims that: "'With its Fusion program, AMD hopes to deliver multicore products using different kinds of processing blocks. A GPU, for example, will excel in multiple parallel computational tasks, while the CPU will take on heavy number-crunching duties. The Fusion-based processors, with the CPU and GPU integrated in a single architecture, should make the life of software programmers and application developers much easier,' Rivas added."
Preliminary information
- A heterogeneous multicore microprocessor architecture, combining a general purpose processing core(s) and basic graphics core(s) into one processor package, with different clocks for the graphics core and the central processing core
- Four platforms focus on the four different aspects of usage
- General Purpose
- Data Centric
- Graphics Centric
- Media Centric
- The Fusion series processor will see new modular design methodology named "M-SPACE", such that design of future multi-core processors will have a wider range of combinations, as well as gaining enhanced flexibility, thus to minimize the architectural changes for different combinations of components. Benefitted from this initiative by AMD, graphics core can be changed without much re-design of the whole core
- Fusion products will include at least 16 PCI Express (presumably version 3.0) lanes
- The implementation of UVD in silicon for full hardware decoding of MPEG2, VC-1 and H.264 video streams on supported software
- The first Z-RAM design on a 45 nm fabrication process node was completed in 2006 , together with the renewal of Z-RAM license. This coincides with the process node that Fusion processors are expected to be fabricated around the timeframe. This also coincides with the AMD official roadmap for larger L3 caches after 2009. Thus it was rumoured that AMD will likely to feature Z-RAM for larger L3 cache in Fusion products.
- A new set of instructions and development libraries for Fusion were being developed , and was revealed to be a new iteration of SSE, named SSE5, which is announced on the August 30, 2007.
- According to Dave Orton, Fusion will have 10% more pins than a "normal CPU" but he failed to further elaborate on what is a "normal CPU".
- Employ Socket FS1 , and two other sockets so that each targeted at different products, Socket FS1 is for mobile parts, another for desktop products and the other server processors.
Implementations
Two implementations were announced publicly during AMD events.
Falcon
- Codenamed the Falcon family
- Announced in AMD Technology Analyst Day July 2007
- Incorporation with GPU cores
- Target market:
- Originally planned with the codenamed Bulldozer processor cores focusing on desktop market with TDP of 10 to 100 Watts
- An option to be implemented into mobile phones, UMPC and small multimedia devices , with the codenamed Bobcat processor core focusing on low power consumption (1 to 10 Watts TDP) computations for handheld devices such as UMPC
Swift
- The plan was later changed to bring the first product of Fusion (codenamed Swift )
- Announced in AMD Financial Analyst Day December 2007
- Based on the codenamed Stars CPU cores (K10 architecture) made on 45 nm process instead of Bulldozer and Bobcat cores
- Aimed at notebook market
- Native CPU die with a GPU core on the same package , implementing Socket FS1, with two variants :
- White Swift: Single CPU core
- Black Swift: Dual CPU core
- Support for DDR3
- Incorporation of full DirectX-compliant GPU core(s): RV710-level, codenamed Kong
- Unified Shaders architecture
- UVD technology for hardware video decoding
- ATI Hybrid Graphics Technology: PowerXpress and Hybrid CrossFire X
- TDP: 5-8 W (load), 0.6-0.8 W (idle)
- Codenamed Onion, new interconnect
- Codenamed Garlic, new memory interface for reduced memory reading latencies of the GPU
Media discussions
- - an interview with Henri Richard
-
Anticipated competitors
- Nehalem, Intel's one to eight core processor microarchitecture possibly including an integrated graphics core .
- VIA CoreFusion, a VIA product focused on low-power consumption computing market.
See also
External links
|
| |
|
|
