22 nanometer
Encyclopedia
The 22 nanometer
(22 nm) node is the CMOS
process step following 32 nm
. It was introduced by semiconductor
companies in 2011. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell is around 22 nm. The exact naming of this technology node comes from the International Technology Roadmap for Semiconductors
(ITRS).
The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm, which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point.
Since the 32 nm half-pitch already requires using double patterning
, in conjunction with hyper-NA (numerical aperture
) immersion lithography
tools, this approach will continue to be used at the 22 nm half-pitch, to which it can be scaled.
Some predictions for the 22 nm node come from the ITRS. For example, it is predicted that silicon devices will no longer be planar
, but will require ultrathin sections mostly surrounded on the sides by gates. The silicon body in each section is fully depleted, i.e., the free charge carrier concentration is deliberately suppressed. The sections basically protrude as fins from the surface (sometimes these are known as FinFETs). The creation of fins is a new challenge for the semiconductor industry, which has become accustomed to building transistors on a flat silicon surface.
According to the ITRS, the 22 nm node also marks the first time where the pre-metal dielectric, separating the transistor from the first metal layer, is a porous low-k
material, replacing traditional, denser CVD
silicon dioxide. The introduction of a porous material closer to the front end presents numerous integration challenges. In particular, the extent of plasma damage to low-k materials is typically 20 nm thick, but can also go up to approximately 100 nm.
The successor to 22 nm technology will be 16 nm
technology per ITRS.
, STMicroelectronics
, Toshiba
, and the College of Nanoscale Science and Engineering
(CNSE) announced that they jointly developed and manufactured a 22 nm SRAM
cell, built on a traditional six-transistor
design on a 300 mm wafer, which had a memory cell size of just 0.1 μm
2. The cell was printed using immersion lithography
.
The 22 nm node may be the first time where the gate length is not necessarily smaller than the technology mode designation. For example, a 25 nm gate length would be typical for the 22 nm node.
On September 22, 2009, during the Intel Developer Forum Fall 2009, Intel showed a 22 nm wafer
and announced that chips with 22 nm technology would be available in the second half of 2011. SRAM cell size is said to be 0.092 μm
2, smallest reported to date.
On January 3, 2010, Intel and Micron Technology Inc. announced the first in a family of 25 nm NAND devices.
On May 2, 2011, Intel announced its first 22 nm microprocessor, codenamed Ivy Bridge, using a technology called 3-D Tri-Gate.
On October 19, 2011, Intel CEO Paul Otellini confirmed that Ivy Bridge 22 nm processor volume production has already begun.
announced that they are shipping 24 nm flash memory NAND devices.
In 2010, Hynix Semiconductor
announced that it could produce a 26 nm flash chip with 64 Gb capacity; Intel Corp. and Micron Technology had by then already developed the technology themselves.
Nanometre
A nanometre is a unit of length in the metric system, equal to one billionth of a metre. The name combines the SI prefix nano- with the parent unit name metre .The nanometre is often used to express dimensions on the atomic scale: the diameter...
(22 nm) node is the CMOS
CMOS
Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...
process step following 32 nm
32 nanometer
The 32 nm process is the step following the 45 nanometer process in CMOS semiconductor device fabrication. 32 nanometer refers to the average half-pitch of a memory cell at this technology level...
. It was introduced by semiconductor
Semiconductor
A semiconductor is a material with electrical conductivity due to electron flow intermediate in magnitude between that of a conductor and an insulator. This means a conductivity roughly in the range of 103 to 10−8 siemens per centimeter...
companies in 2011. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell is around 22 nm. The exact naming of this technology node comes from the International Technology Roadmap for Semiconductors
International Technology Roadmap for Semiconductors
The International Technology Roadmap for Semiconductors is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry Associations of the US, Europe, Japan, South Korea and...
(ITRS).
The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm, which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point.
Since the 32 nm half-pitch already requires using double patterning
Double patterning
Multiple patterning is a class of technologies for manufacturing integrated circuits , developed for photolithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected...
, in conjunction with hyper-NA (numerical aperture
Numerical aperture
In optics, the numerical aperture of an optical system is a dimensionless number that characterizes the range of angles over which the system can accept or emit light. By incorporating index of refraction in its definition, NA has the property that it is constant for a beam as it goes from one...
) immersion lithography
Immersion lithography
Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive index greater than one. The resolution is increased by a factor...
tools, this approach will continue to be used at the 22 nm half-pitch, to which it can be scaled.
Some predictions for the 22 nm node come from the ITRS. For example, it is predicted that silicon devices will no longer be planar
Planar
In computer graphics, planar is the method of representing pixel colours with several bitplanes of RAM. Each bit in a bitplane is related to one pixel on the screen...
, but will require ultrathin sections mostly surrounded on the sides by gates. The silicon body in each section is fully depleted, i.e., the free charge carrier concentration is deliberately suppressed. The sections basically protrude as fins from the surface (sometimes these are known as FinFETs). The creation of fins is a new challenge for the semiconductor industry, which has become accustomed to building transistors on a flat silicon surface.
According to the ITRS, the 22 nm node also marks the first time where the pre-metal dielectric, separating the transistor from the first metal layer, is a porous low-k
Low-K
In semiconductor manufacturing, a low-κ dielectric is a material with a small dielectric constant relative to silicon dioxide. Although the proper symbol for the dielectric constant is the Greek letter κ , in conversation such materials are referred to as being "low-k" rather than "low-κ"...
material, replacing traditional, denser CVD
Chemical vapor deposition
Chemical vapor deposition is a chemical process used to produce high-purity, high-performance solid materials. The process is often used in the semiconductor industry to produce thin films. In a typical CVD process, the wafer is exposed to one or more volatile precursors, which react and/or...
silicon dioxide. The introduction of a porous material closer to the front end presents numerous integration challenges. In particular, the extent of plasma damage to low-k materials is typically 20 nm thick, but can also go up to approximately 100 nm.
The successor to 22 nm technology will be 16 nm
16 nanometer
The 16 nanometer node is the technology node following the 22 nm node. The exact naming of the technology nodes comes from the International Technology Roadmap for Semiconductors . By conservative ITRS estimates the 16 nm technology is projected to be reached by semiconductor companies in the...
technology per ITRS.
Technology demos
On August 18, 2008, AMD, Freescale, IBMIBM
International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
, STMicroelectronics
STMicroelectronics
STMicroelectronics is an Italian-French electronics and semiconductor manufacturer headquartered in Geneva, Switzerland.While STMicroelectronics corporate headquarters and the headquarters for EMEA region are based in Geneva, the holding company, STMicroelectronics N.V. is registered in Amsterdam,...
, Toshiba
Toshiba
is a multinational electronics and electrical equipment corporation headquartered in Tokyo, Japan. It is a diversified manufacturer and marketer of electrical products, spanning information & communications equipment and systems, Internet-based solutions and services, electronic components and...
, and the College of Nanoscale Science and Engineering
College of Nanoscale Science and Engineering
The College of Nanoscale Science and Engineering , on the campus of the University at Albany is a global education, research, development and technology deployment resource for students and researchers in nanotechnology...
(CNSE) announced that they jointly developed and manufactured a 22 nm SRAM
Static random access memory
Static random-access memory is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM , it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit...
cell, built on a traditional six-transistor
Transistor
A transistor is a semiconductor device used to amplify and switch electronic signals and power. It is composed of a semiconductor material with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals changes the current...
design on a 300 mm wafer, which had a memory cell size of just 0.1 μm
Micrometre
A micrometer , is by definition 1×10-6 of a meter .In plain English, it means one-millionth of a meter . Its unit symbol in the International System of Units is μm...
2. The cell was printed using immersion lithography
Immersion lithography
Immersion lithography is a photolithography resolution enhancement technique for manufacturing integrated circuits that replaces the usual air gap between the final lens and the wafer surface with a liquid medium that has a refractive index greater than one. The resolution is increased by a factor...
.
The 22 nm node may be the first time where the gate length is not necessarily smaller than the technology mode designation. For example, a 25 nm gate length would be typical for the 22 nm node.
On September 22, 2009, during the Intel Developer Forum Fall 2009, Intel showed a 22 nm wafer
Wafer (electronics)
A wafer is a thin slice of semiconductor material, such as a silicon crystal, used in the fabrication of integrated circuits and other microdevices...
and announced that chips with 22 nm technology would be available in the second half of 2011. SRAM cell size is said to be 0.092 μm
Micrometre
A micrometer , is by definition 1×10-6 of a meter .In plain English, it means one-millionth of a meter . Its unit symbol in the International System of Units is μm...
2, smallest reported to date.
On January 3, 2010, Intel and Micron Technology Inc. announced the first in a family of 25 nm NAND devices.
On May 2, 2011, Intel announced its first 22 nm microprocessor, codenamed Ivy Bridge, using a technology called 3-D Tri-Gate.
On October 19, 2011, Intel CEO Paul Otellini confirmed that Ivy Bridge 22 nm processor volume production has already begun.
Shipping Devices
On August 31, 2010, ToshibaToshiba
is a multinational electronics and electrical equipment corporation headquartered in Tokyo, Japan. It is a diversified manufacturer and marketer of electrical products, spanning information & communications equipment and systems, Internet-based solutions and services, electronic components and...
announced that they are shipping 24 nm flash memory NAND devices.
In 2010, Hynix Semiconductor
Hynix
Hynix Semiconductor Inc. chips and flash memory chips. Founded in 1983, Hynix is the world's second-largest memory chipmaker, the largest being Samsung Electronics. Formerly known as Hyundai Electronics, the company has manufacturing sites in Korea, the U.S., China and Taiwan...
announced that it could produce a 26 nm flash chip with 64 Gb capacity; Intel Corp. and Micron Technology had by then already developed the technology themselves.