1T-SRAM
Encyclopedia
1T-SRAM is a pseudostatic random-access memory
(RAM) technology introduced by MoSys, Inc., which offers a high-density alternative to traditional static random access memory
(SRAM) in embedded memory applications. Mosys uses a single-transistor storage cell (bit cell) like dynamic random access memory
(DRAM), but surrounds the bit cell with control circuitry that makes the memory functionally equivalent to SRAM (the controller hides all DRAM-specific operations such as precharging and refresh). 1T-SRAM (and PSRAM
in general) has a standard single-cycle SRAM interface and appears to the surrounding logic just as an SRAM would.
Due to its one-transistor bit cell, 1T-SRAM is smaller than conventional (six-transistor, or “6T”) SRAM, and closer in size and density to embedded DRAM (eDRAM
). At the same time, 1T-SRAM has performance comparable to SRAM at multi-megabit densities, uses less power than eDRAM and is manufactured in a standard CMOS logic process like conventional SRAM.
MoSyS markets 1T-SRAM as physical IP
for embedded (on-die) use in System-on-a-chip
(SOC) applications. It is available on a variety of foundry processes, including Chartered, SMIC, TSMC, and UMC. Some engineers use the terms 1T-SRAM and "embedded DRAM" interchangeably, as some foundries provide Mosys's 1T-SRAM as “eDRAM”. However, other foundries provide 1T-SRAM as a distinct offering.
. In the event of repeated accesses to one bank, which would not allow time for refresh cycles, there are two options: either the accesses are all to different rows, in which case all rows will be refreshed automatically, or some rows are accessed repeatedly. In the latter case, the cache provides the data and allows time for an unused row of the active bank to be refreshed.
There have been four generations of 1T-SRAM:
Original 1T-SRAM : About half the size of 6T-SRAM, less than half the power.
1T-SRAM-M : Variant with lower standby power consumption, for applications such as cell phones.
1T-SRAM-R : Incorporates ECC for lower soft error
rates. To avoid an area penalty, it uses smaller bit cells, which have an inherently higher error rate, but the ECC more than makes up for that.
1T-SRAM-Q : This "quad-density" version uses a slightly non-standard fabrication process to produce a smaller folded capacitor, allowing the memory size to be halved again over 1T-SRAM-R. This does add slightly to wafer production costs, but does not interfere with logic transistor fabrication the way conventional DRAM capacitor construction does.
s and processing steps, offsetting the cost of a larger 1T-SRAM die. Also, some of those steps require very high temperatures and must take place after the logic transistors are formed, possibly damaging them.
1T-SRAM is also available in device (IC) form. The Nintendo GameCube
was the first video game system to use 1T-SRAM as a primary (main) memory storage; the GameCube possesses several dedicated 1T-SRAM devices. 1T-SRAM is also used in the successor to the GameCube, Nintendo
's Wii
console.
Note that this is not the same as 1T DRAM, which is a "capacitorless" DRAM cell built using the parasitic channel capacitor of SOI
transistors rather than a discrete capacitor.http://legwww.epfl.ch/ekv/mos-ak/wroclaw/MOS-AK_JMS.pdf
MoSys claims the following sizes for 1T-SRAM arrays:
) describes a similar system for hiding DRAM refresh using an SRAM cache.
Random-access memory
Random access memory is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order with a worst case performance of constant time. Strictly speaking, modern types of DRAM are therefore not random access, as data is read in...
(RAM) technology introduced by MoSys, Inc., which offers a high-density alternative to traditional static random access memory
Static random access memory
Static random-access memory is a type of semiconductor memory where the word static indicates that, unlike dynamic RAM , it does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit...
(SRAM) in embedded memory applications. Mosys uses a single-transistor storage cell (bit cell) like dynamic random access memory
Dynamic random access memory
Dynamic random-access memory is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1...
(DRAM), but surrounds the bit cell with control circuitry that makes the memory functionally equivalent to SRAM (the controller hides all DRAM-specific operations such as precharging and refresh). 1T-SRAM (and PSRAM
Dynamic random access memory
Dynamic random-access memory is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1...
in general) has a standard single-cycle SRAM interface and appears to the surrounding logic just as an SRAM would.
Due to its one-transistor bit cell, 1T-SRAM is smaller than conventional (six-transistor, or “6T”) SRAM, and closer in size and density to embedded DRAM (eDRAM
EDRAM
eDRAM stands for "embedded DRAM", a capacitor-based dynamic random access memory integrated on the same die as an ASIC or processor. The cost-per-bit is higher than for stand-alone DRAM chips but in many applications the performance advantages of placing the eDRAM on the same chip as the processor...
). At the same time, 1T-SRAM has performance comparable to SRAM at multi-megabit densities, uses less power than eDRAM and is manufactured in a standard CMOS logic process like conventional SRAM.
MoSyS markets 1T-SRAM as physical IP
Intellectual property
Intellectual property is a term referring to a number of distinct types of creations of the mind for which a set of exclusive rights are recognized—and the corresponding fields of law...
for embedded (on-die) use in System-on-a-chip
System-on-a-chip
A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
(SOC) applications. It is available on a variety of foundry processes, including Chartered, SMIC, TSMC, and UMC. Some engineers use the terms 1T-SRAM and "embedded DRAM" interchangeably, as some foundries provide Mosys's 1T-SRAM as “eDRAM”. However, other foundries provide 1T-SRAM as a distinct offering.
Technology
1T SRAM is built as an array of small banks (typically 128 rows × 256 bits/row, 32 Kbits in total) coupled to a bank-sized SRAM cache and an intelligent controller. Although space-inefficient compared to regular DRAM, the short word lines allow much higher speeds, so the array can do a full sense and precharge (RAS cycle) per access, providing high-speed random access. Each access is to one bank, allowing unused banks to be refreshed at the same time. Additionally, each row read out of the active bank is copied to the bank-sized SRAM cacheCache
In computer engineering, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere...
. In the event of repeated accesses to one bank, which would not allow time for refresh cycles, there are two options: either the accesses are all to different rows, in which case all rows will be refreshed automatically, or some rows are accessed repeatedly. In the latter case, the cache provides the data and allows time for an unused row of the active bank to be refreshed.
There have been four generations of 1T-SRAM:
Original 1T-SRAM : About half the size of 6T-SRAM, less than half the power.
1T-SRAM-M : Variant with lower standby power consumption, for applications such as cell phones.
1T-SRAM-R : Incorporates ECC for lower soft error
Soft error
In electronics and computing, a soft error is an error in a signal or datum which is wrong. Errors may be caused by a defect, usually understood either to be a mistake in design or construction, or a broken component. A soft error is also a signal or datum which is wrong, but is not assumed to...
rates. To avoid an area penalty, it uses smaller bit cells, which have an inherently higher error rate, but the ECC more than makes up for that.
1T-SRAM-Q : This "quad-density" version uses a slightly non-standard fabrication process to produce a smaller folded capacitor, allowing the memory size to be halved again over 1T-SRAM-R. This does add slightly to wafer production costs, but does not interfere with logic transistor fabrication the way conventional DRAM capacitor construction does.
Comparison with other embedded memory technologies
1T-SRAM has speed comparable to 6T-SRAM (at multi-megabit densities). It is significantly faster speed than eDRAM, and the "quad-density" variant is only slightly larger (10–15% is claimed). On most foundry processes, designs with eDRAM require additional (and costly) maskPhotomask
A photomask is an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. They are commonly used in photolithography.-Overview:...
s and processing steps, offsetting the cost of a larger 1T-SRAM die. Also, some of those steps require very high temperatures and must take place after the logic transistors are formed, possibly damaging them.
1T-SRAM is also available in device (IC) form. The Nintendo GameCube
Nintendo GameCube
The , officially abbreviated to NGC in Japan and GCN in other regions, is a sixth generation video game console released by Nintendo on September 15, 2001 in Japan, November 18, 2001 in North America, May 3, 2002 in Europe, and May 17, 2002 in Australia...
was the first video game system to use 1T-SRAM as a primary (main) memory storage; the GameCube possesses several dedicated 1T-SRAM devices. 1T-SRAM is also used in the successor to the GameCube, Nintendo
Nintendo
is a multinational corporation located in Kyoto, Japan. Founded on September 23, 1889 by Fusajiro Yamauchi, it produced handmade hanafuda cards. By 1963, the company had tried several small niche businesses, such as a cab company and a love hotel....
's Wii
Wii
The Wii is a home video game console released by Nintendo on November 19, 2006. As a seventh-generation console, the Wii primarily competes with Microsoft's Xbox 360 and Sony's PlayStation 3. Nintendo states that its console targets a broader demographic than that of the two others...
console.
Note that this is not the same as 1T DRAM, which is a "capacitorless" DRAM cell built using the parasitic channel capacitor of SOI
Silicon on insulator
Silicon on insulator technology refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance...
transistors rather than a discrete capacitor.http://legwww.epfl.ch/ekv/mos-ak/wroclaw/MOS-AK_JMS.pdf
MoSys claims the following sizes for 1T-SRAM arrays:
| Process node | 250 nm | 180 nm | 130 nm | 90 nm | 65 nm | 45 nm | |
|---|---|---|---|---|---|---|---|
| 6T-SRAM | bit cell | 7.56 | 4.65 | 2.43 | 1.36 | 0.71 | 0.34 |
| with overhead | 11.28 | 7.18 | 3.73 | 2.09 | 1.09 | 0.52 | |
| 1T-SRAM | bit cell | 3.51 | 1.97 | 1.10 | 0.61 | 0.32 | 0.15 |
| with overhead | 7.0 | 3.6 | 1.9 | 1.1 | 0.57 | 0.28 | |
| 1T-SRAM-Q | bit cell | 0.50 | 0.28 | 0.15 | 0.07 | ||
| with overhead | 1.05 | 0.55 | 0.29 | 0.14 |
See also
US Patent 7,146,454 "Hiding refresh in 1T-SRAM Architecture"* (by Cypress SemiconductorCypress Semiconductor
Cypress Semiconductor Corporation is a Silicon Valley-based semiconductor design and manufacturing company founded by T. J. Rodgers and others from Advanced Micro Devices. It was formed in 1982 with backing by Sevin Rosen and went public in 1986. The company initially focused on the design and...
) describes a similar system for hiding DRAM refresh using an SRAM cache.