NMOS logic
nMOS logic uses n-type metal-oxide-semiconductor
field effect transistors to implement
logic gates and other
digital circuits. nMOS transistors have three modes of operation: cut-off, triode, and saturation .
The n-type MOSFETs are arranged in a so-called "pull-down network" between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.
Encyclopedia
nMOS logic uses n-type metal-oxide-semiconductor
field effect transistors to implement
logic gates and other
digital circuits. nMOS transistors have three modes of operation: cut-off, triode, and saturation .
The n-type MOSFETs are arranged in a so-called "pull-down network" between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.
As an example, here is a
NOR gate in nMOS logic. If either input A or input B is high , the respective MOS transistor acts as a very low resistance between the output and the negative supply, forcing the output to be low . When both A and B are high, both transistors are conductive, creating an even lower resistance path to ground. The only case where the output is high is when both transistors are off, which occurs only when both A and B are low, thus satisfying the truth table of a NOR gate:
| A | B | A NOR B |
|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
While nMOS logic is easy to design and manufacture , it has several shortcomings as well. The worst problem is that a DC current flows through an nMOS logic gate when the PDN is active, that is whenever the output is low. This leads to static power dissipation even when the circuit sits idle.
Also, nMOS circuits are slow to transition from low to high. When transitioning from high to low, the transistors provide low resistance, and the capacitative charge at the output drains away very quickly. But the resistance between the output and the positive supply rail is much greater, so the low to high transition takes longer. Using a resistor of lower value will speed up the process but also increases static power dissipation.
Additionally, the asymmetric input logic levels make nMOS circuits susceptible to noise.
These disadvantages are why nMOS logic was supplanted by
CMOS logic both in low-power and in high-speed digital circuits, such as
microprocessors, during the 1980s.
